A test rack includes two or more memory device test boards where each memory device test boards includes two or more memory device test resources. Each of the two or more memory device test boards includes a separate processing device allocated to the memory device test resources of a corresponding memory device test boards. A processing device of a test board detects that a first memory sub-system has engaged with a first memory device test resource of the corresponding memory device test board. The processing device identifies a first test to be performed for a first memory device of the first memory sub-system, where the first test includes one or more first test instructions to be executed in performance of the first test. The processing device causes the one or more first test instructions to be transmitted to the first memory sub-system, where the first test is performed by the one or more first test instructions executing at the first memory sub-system.