公开(公告)号：US12142336B2

公开(公告)日：2024-11-12

申请号：US17716972

申请日：2022-04-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Gary D. Hamor ,  Michael R. Spica ,  Donald Shepard ,  Patrick Caraher ,  João Elmiro da Rocha Chaves

IPC: G11C29/44 ,  G06F9/50 ,  G11C29/22 ,  G11C29/36 ,  G11C29/56

Abstract: A detection is made by a processing device allocated to a memory device test board of a distributed test platform that a memory sub-system has engaged with a memory device test resource of the memory device test board. A test is identified to be performed for a memory device of the memory sub-system. The test includes first instructions to be executed by a memory sub-system controller of the memory sub-system in performance of the test and second instructions to be executed by the processing device in performance of the test. The second instructions are to cause one or more test condition components of the memory device test resource to generate one or more test conditions to be applied to the memory device while the memory sub-system executes the first instructions. Responsive to a transmission of the first instructions to the memory sub-system controller, the second instructions are executed.

公开(公告)号：US20220230700A1

公开(公告)日：2022-07-21

申请号：US17716972

申请日：2022-04-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Gary D. Hamor ,  Michael R. Spica ,  Donald Shepard ,  Patrick Caraher ,  João Elmiro da Rocha Chaves

IPC: G11C29/44 ,  G11C29/56 ,  G11C29/36 ,  G06F9/50 ,  G11C29/22

Abstract: A detection is made by a processing device allocated to a memory device test board of a distributed test platform that a memory sub-system has engaged with a memory device test resource of the memory device test board. A test is identified to be performed for a memory device of the memory sub-system. The test includes first instructions to be executed by a memory sub-system controller of the memory sub-system in performance of the test and second instructions to be executed by the processing device in performance of the test. The second instructions are to cause one or more test condition components of the memory device test resource to generate one or more test conditions to be applied to the memory device while the memory sub-system executes the first instructions. Responsive to a transmission of the first instructions to the memory sub-system controller, the second instructions are executed.

公开(公告)号：US11328789B2

公开(公告)日：2022-05-10

申请号：US16719707

申请日：2019-12-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Gary D. Hamor ,  Michael R. Spica ,  Donald Shepard ,  Patrick Caraher ,  João Elmiro da Rocha Chaves

IPC: G11C29/44 ,  G11C29/56 ,  G11C29/36 ,  G06F9/50 ,  G11C29/22

Abstract: A test rack includes two or more memory device test boards where each memory device test boards includes two or more memory device test resources. Each of the two or more memory device test boards includes a separate processing device allocated to the memory device test resources of a corresponding memory device test boards. A processing device of a test board detects that a first memory sub-system has engaged with a first memory device test resource of the corresponding memory device test board. The processing device identifies a first test to be performed for a first memory device of the first memory sub-system, where the first test includes one or more first test instructions to be executed in performance of the first test. The processing device causes the one or more first test instructions to be transmitted to the first memory sub-system, where the first test is performed by the one or more first test instructions executing at the first memory sub-system.

公开(公告)号：US20210193250A1

公开(公告)日：2021-06-24

申请号：US16719707

申请日：2019-12-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Gary D. Hamor ,  Michael R. Spica ,  Donald Shepard ,  Patrick Caraher ,  João Elmiro da Rocha Chaves

IPC: G11C29/44 ,  G11C29/56 ,  G11C29/22 ,  G11C29/36 ,  G06F9/50

Abstract: A test rack includes two or more memory device test boards where each memory device test boards includes two or more memory device test resources. Each of the two or more memory device test boards includes a separate processing device allocated to the memory device test resources of a corresponding memory device test boards. A processing device of a test board detects that a first memory sub-system has engaged with a first memory device test resource of the corresponding memory device test board. The processing device identifies a first test to be performed for a first memory device of the first memory sub-system, where the first test includes one or more first test instructions to be executed in performance of the first test. The processing device causes the one or more first test instructions to be transmitted to the first memory sub-system, where the first test is performed by the one or more first test instructions executing at the first memory sub-system.