Invention Grant
- Patent Title: Top gate recessed channel CMOS thin film transistor in the back end of line and methods of fabrication
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Application No.: US16728887Application Date: 2019-12-27
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Publication No.: US11328988B2Publication Date: 2022-05-10
- Inventor: Gilbert Dewey , Ryan Keech , Cory Bomberger , Cheng-Ying Huang , Ashish Agrawal , Willy Rachmady , Anand Murthy
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Essential Patents Group, LLP
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L23/522 ; H01L21/768 ; H01L21/762

Abstract:
A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.
Public/Granted literature
- US20210202378A1 TOP GATE RECESSED CHANNEL CMOS THIN FILM TRANSISTOR IN THE BACK END OF LINE AND METHODS OF FABRICATION Public/Granted day:2021-07-01
Information query
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