Invention Grant
- Patent Title: Configuration or data caching for programmable logic device
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Application No.: US15868627Application Date: 2018-01-11
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Publication No.: US11334263B2Publication Date: 2022-05-17
- Inventor: Scott J. Weber , David Greenhill , Sean R. Atsatt , Ravi Prakash Gutala , Aravind Raghavendra Dasu , Jun Pin Tan
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Fletcher Yoder P.C.
- Main IPC: G06F3/06
- IPC: G06F3/06 ; G06F12/0802 ; G06F12/0873 ; H03K19/17736 ; G11C7/22 ; G11C5/02 ; G06F12/0875 ; G06F30/34 ; G11C5/04 ; G11C7/10

Abstract:
An integrated circuit device may cache configuration data to enable rapid configuration from fabric cache memory. The integrated circuit device may include programmable logic fabric having configuration memory and programmable logic elements controlled by the configuration memory, and sector-aligned memory apart from the programmable logic fabric. A first sector of the configuration memory may be programmed with first configuration data. The sector-aligned memory may include a first sector of sector-aligned memory that may cache the first configuration data while the configuration memory is programmed with the first configuration data a first time. A second sector of sector-aligned memory may cache second configuration data for a second sector of the configuration memory in parallel while the first sector of sector-aligned memory caches the first configuration data for the first sector of the configuration memory.
Public/Granted literature
- US20190042127A1 Configuration or Data Caching for Programmable Logic Device Public/Granted day:2019-02-07
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