公开(公告)号：US12265772B2

公开(公告)日：2025-04-01

申请号：US17850560

申请日：2022-06-27

Applicant: Intel Corporation

Inventor： Scott Weber ,  Sean R. Atsatt ,  David Goldman

IPC: G06F30/34 ,  G06F111/04

Abstract: Methods and apparatus for extracting a setting of configuration bits to create an exclusion configuration for providing protection against peek and poke attacks in a multi-tenant usage model of a configurable device is provided. The device may host multiple parties that do not trust each other. Peek and poke attacks are orchestrated by tapping (peeking) and driving (poking) wires associated with other parties. Such attacks may be disabled by excluding the settings of configuration bits that would allow these attacks by other parties. This set of configuration bits that should be excluded for preventing all peek and poke attacks creates the exclusion configuration. Methods are described that disable a particular class of peek and/or poke attacks through the use of partial reconfiguration. Methods and apparatus are described to dynamically detect peek and/or poke attacks.

公开(公告)号：US11562101B2

公开(公告)日：2023-01-24

申请号：US16020805

申请日：2018-06-27

Applicant: Intel Corporation

Inventor： Scott J. Weber ,  Sean R. Atsatt ,  Andrew Martyn Draper ,  David Samuel Goldman

IPC: H04L9/30 ,  H04L29/06 ,  G06F21/76 ,  H03M13/27 ,  G06F7/58 ,  G06F21/73

Abstract: A programmable logic device verifies that configuration data permissibly programs the programmable logic device. The programmable logic device includes a programmable fabric having partitions to be programmed by the configuration data, a secure device manager that may generate masks based on the configuration data, and a local sector manager. The masks determine that the configuration data is configured to permissibly program the permitted partitions or that the permitted partitions have been permissibly programmed. The local sector manager applies the masks to generate an interleaved result, compares the interleaved result to an expected result, and sends an indication that the configuration data is configured to permissibly program the permitted partitions or permissibly programmed the permitted partitions in response to determining that the interleaved result is the expected result, or sends an alert to stop programming in response to determining that the interleaved result is not the expected result.

公开(公告)号：US20220116044A1

公开(公告)日：2022-04-14

申请号：US17556917

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Sharath Raghava ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy ,  Harsha Gupta ,  James Ball ,  Kavitha Prasad ,  Sean R. Atsatt

IPC: H03K19/17736 ,  H03K19/17796 ,  H04L41/5019

Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.

公开(公告)号：US11206024B2

公开(公告)日：2021-12-21

申请号：US17033524

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Sharath Raghava ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy ,  Harsha Gupta ,  James Ball ,  Kavitha Prasad ,  Sean R. Atsatt

IPC: H03K19/177 ,  H03K19/17736 ,  H03K19/17796 ,  H04L12/24

Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.

公开(公告)号：US10936511B2

公开(公告)日：2021-03-02

申请号：US16232834

申请日：2018-12-26

Applicant: Intel Corporation

Inventor： Sean R. Atsatt ,  Chee Hak Teh

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/28

Abstract: Systems and methods for providing capability of access to distributed memory blocks using a global address scheme in a programmable logic device. Each of the distributed memory blocks includes routing circuitry that receives data, and in a first mode, decodes whether the data is intended for a respective distributed memory block. In a second mode, the data may bypass routing circuitry. Furthermore, the data may be received at the distributed memory block via cascade connections of distributed memory blocks in a column and/or via register in the programmable fabric of the programmable logic device.

公开(公告)号：US10587273B2

公开(公告)日：2020-03-10

申请号：US16235926

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Sean R. Atsatt ,  Herman Henry Schmit

IPC: H03K19/177 ,  H03K19/17796 ,  H03K19/17792 ,  H03K19/17736 ,  H03K19/17724

Abstract: An integrated circuit may include multiple programmable logic regions and a first plurality of routers. Each of the first plurality of routers is coupled to a respective region of a first portion of the programmable logic regions, and each of the first portion of the plurality of regions transmits configuration data to a first set of adjacent regions of the first portion of regions. The integrated circuit may also include a second plurality of routers, and each of the second plurality of routers is coupled to a respective region of a second portion of the regions. Each of the second portion of the regions transmits the configuration data to a second set of adjacent regions of the first portion of regions. The integrated circuit may also include a voltage regulator that distributes a voltage to each of the regions.

公开(公告)号：US20190050604A1

公开(公告)日：2019-02-14

申请号：US16020805

申请日：2018-06-27

Applicant: Intel Corporation

Inventor： Scott J. Weber ,  Sean R. Atsatt ,  Andrew Martyn Draper ,  David Goldman

IPC: G06F21/76 ,  G06F21/73 ,  G06F7/58 ,  H03M13/27

Abstract: A programmable logic device verifies that configuration data permissibly programs the programmable logic device. The programmable logic device includes a programmable fabric having partitions to be programmed by the configuration data, a secure device manager that may generate masks based on the configuration data, and a local sector manager. The masks determine that the configuration data is configured to permissibly program the permitted partitions or that the permitted partitions have been permissibly programmed. The local sector manager applies the masks to generate an interleaved result, compares the interleaved result to an expected result, and sends an indication that the configuration data is configured to permissibly program the permitted partitions or permissibly programmed the permitted partitions in response to determining that the interleaved result is the expected result, or sends an alert to stop programming in response to determining that the interleaved result is not the expected result.

公开(公告)号：US12153866B2

公开(公告)日：2024-11-26

申请号：US18327045

申请日：2023-05-31

Applicant: Intel Corporation

Inventor： Chee Hak Teh ,  Ankireddy Nalamalpu ,  MD Altaf Hossain ,  Dheeraj Subbareddy ,  Sean R. Atsatt ,  Lai Guan Tang

IPC: G06F30/34 ,  G06F15/78 ,  H03K19/17736 ,  H03K19/17796 ,  H04L12/43

Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.

公开(公告)号：US20230306173A1

公开(公告)日：2023-09-28

申请号：US18327045

申请日：2023-05-31

Applicant: Intel Corporation

Inventor： Chee Hak Teh ,  Ankireddy Nalamalpu ,  MD Altaf Hossain ,  Dheeraj Subbareddy ,  Sean R. Atsatt ,  Lai Guan Tang

IPC: G06F30/34 ,  H03K19/17736 ,  H04L12/43 ,  G06F15/78 ,  H03K19/17796

CPC classification number: G06F30/34 ,  H03K19/17744 ,  H04L12/43 ,  G06F15/7825 ,  H03K19/17796

Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.

公开(公告)号：US11700002B2

公开(公告)日：2023-07-11

申请号：US17556917

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Sharath Raghava ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy ,  Harsha Gupta ,  James Ball ,  Kavitha Prasad ,  Sean R. Atsatt

IPC: H04L12/28 ,  H03K19/17736 ,  H03K19/17796 ,  H04L41/5019 ,  H04L41/5003

CPC classification number: H03K19/17736 ,  H03K19/17796 ,  H04L41/5019 ,  H04L41/5003

Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.