Invention Grant
- Patent Title: Tuning of loop orders in blocked dense basic linear algebra subroutines
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Application No.: US16454318Application Date: 2019-06-27
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Publication No.: US11354564B2Publication Date: 2022-06-07
- Inventor: Alexander Heinecke , Evangelos Georganas , Justin Gottschlich
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Hanley, Flight & Zimmerman, LLC
- Main IPC: G06N3/04
- IPC: G06N3/04 ; G06F9/30 ; G06N3/08 ; G06F8/41 ; G06F9/455

Abstract:
An example includes a sequence generator to generate a plurality of sequence pairs, a first one of the sequence pairs including: (i) a first input sequence representing first accesses to first tensors in a first loop nest of a first computer program, and (ii) a first output sequence representing a first tuned loop nest corresponding to the first accesses to the first tensors in the first loop nest; a model trainer to train a recurrent neural network based on the sequence pairs as training data, the recurrent neural network to be trained to tune loop ordering of a second computer program based on a second input sequence representing second accesses to a second tensor in a second loop nest of the second computer program; and a memory interface to store, in memory, a trained model corresponding to the recurrent neural network.
Public/Granted literature
- US20190318225A1 TUNING OF LOOP ORDERS IN BLOCKED DENSE BASIC LINEAR ALGEBRA SUBROUTINES Public/Granted day:2019-10-17
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