- Patent Title: Conductive via of integrated circuitry, memory array comprising strings of memory cells, method of forming a conductive via of integrated circuitry, and method of forming a memory array comprising strings of memory cells
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Application No.: US16987991Application Date: 2020-08-07
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Publication No.: US11355392B2Publication Date: 2022-06-07
- Inventor: Yiping Wang , Jordan D. Greenlee , Collin Howder
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/522 ; H01L27/11565 ; H01L27/11519 ; H01L27/1157 ; H01L27/11521 ; H01L27/11556 ; H01L27/11582
Abstract:
A method used in forming a conductive via of integrated circuitry comprises forming a lining laterally over sidewalk of an elevationally-elongated opening. The lining comprises elemental-form silicon. The elemental-form silicon of an uppermost portion of the lining is ion implanted in the elevationally-elongated opening. The ion-implanted elemental-form silicon of the uppermost portion of the lining is etched selectively relative to the elemental-form silicon of a lower portion of the lining below the uppermost portion that was not subjected to said ion implanting. The elemental-form silicon of the lower portion of the lining is reacted with a metal halide to form elemental-form metal in a lower portion of the elevationally-elongated opening that is the metal from the metal halide. Conductive material in the elevationally-elongated opening is formed atop and directly against the elemental-form metal. Other embodiments, including structure independent of method, are disclosed.
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