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    Memory Circuitry And Method Used In Forming Memory Circuitry
    5.
    发明公开
    Memory Circuitry And Method Used In Forming Memory Circuitry 审中-公开

    公开(公告)号：US20230395513A1

    公开(公告)日：2023-12-07

    申请号：US17865565

    申请日：2022-07-15

    Applicant: Micron Technology, Inc.

    Inventor： Harsh Narendrakumar Jain ,  Yiping Wang ,  Jordan Chess ,  Collin Howder

    IPC: H01L23/535 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11582

    CPC classification number: H01L23/535 ,  H01L23/5283 ,  H01L27/11556 ,  H01L27/11582

    Abstract: A method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers, with the stack extending from a memory-array region into a stair-step region. The stair-step region comprises a flight of stairs in a first vertical cross-section along a first direction. Masking material is formed directly above the flight of stairs. A species is ion implanted into the masking material to form different-composition first and second regions that are directly above individual of the stairs along a second direction that is orthogonal to the first direction. One of the first and the second regions is removed selectively relative to the other of the first and the second regions. After the removing, the other of the first and second regions is used as a mask while etching through one of the first tiers and one of the second tiers in the individual stairs to form multiple different-depth treads in the individual stairs in a second vertical cross-section along the second direction. Other embodiments, including structure, are disclosed.

    METHODS OF FORMING AN APPARATUS INCLUDING LAMINATE SPACER STRUCTURES
    7.
    发明申请
    METHODS OF FORMING AN APPARATUS INCLUDING LAMINATE SPACER STRUCTURES 有权

    公开(公告)号：US20220020748A1

    公开(公告)日：2022-01-20

    申请号：US17449352

    申请日：2021-09-29

    Applicant: Micron Technology, Inc.

    Inventor： Silvia Borsari ,  Stian E. Wood ,  Haoyu Li ,  Yiping Wang

    IPC: H01L27/108 ,  H01L21/768 ,  H01L27/08

    Abstract: An apparatus comprises a conductive structure, another conductive structure, and a laminate spacer structure interposed between the conductive structure and the another conductive structure in a first direction. The laminate spacer structure comprises a dielectric spacer structure, another dielectric spacer structure, and an additional dielectric spacer structure interposed between the dielectric spacer structure and the another dielectric spacer structure. The additional dielectric spacer structure comprises at least one dielectric material, and gas pockets dispersed within the at least one dielectric material. Additional apparatuses, memory devices, electronic systems, and a method of forming an apparatus are also described.

    Memory device including staircase structure having conductive pads
    8.
    发明授权
    Memory device including staircase structure having conductive pads 有权

    公开(公告)号：US12300616B2

    公开(公告)日：2025-05-13

    申请号：US18214911

    申请日：2023-06-27

    Applicant: Micron Technology, Inc.

    Inventor： Alyssa N. Scarbrough ,  Yiping Wang ,  Jordan D. Greenlee ,  John Hopkins

    IPC: H01L23/535 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H10B41/27 ,  H10B43/27

    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a device including tiers of materials located one over another, the tiers of materials including respective memory cells and control gates for the memory cells. The control gates include respective portions that collectively form part of a staircase structure. The staircase structure includes first regions and second regions coupled to the first regions. The second regions include respective sidewalls in which a portion of each of the first regions and a portion of each of the second regions are part of a respective control gate of the control gates. The device also includes conductive pads electrically separated from each other and located on the first regions of the staircase structure, and conductive contacts contacting the conductive pads.

    NAND STAIRCASE LANDING PADS CONVERSION
    10.
    发明公开
    NAND STAIRCASE LANDING PADS CONVERSION 审中-公开

    公开(公告)号：US20240251552A1

    公开(公告)日：2024-07-25

    申请号：US18417709

    申请日：2024-01-19

    Applicant: Micron Technology, Inc.

    Inventor： Mojtaba Asadirad ,  Yiping Wang ,  David H. Wells ,  Matt J. King

    IPC: H10B43/27 ,  H10B41/27

    CPC classification number: H10B43/27 ,  H10B41/27

    Abstract: Methods, systems, and devices for NAND staircase landing pads conversion are described. A memory device may include one or more lateral word line contacts that may couple a word line with a conductive pillar that traverses a stack of materials of the memory device. The use of the lateral word line contact may allow for a conductive pillar to be coupled with a target word line without requiring an end of the conductive pillar to be placed directly on the word line. Additionally, the memory architecture described herein may allow for the target word line to be coupled with CMOS circuitry via a first conductive pillar without the use of a second conductive pillar, as the first conductive pillar may traverse the stack of materials and be coupled with the CMOS circuitry. Therefore, total quantity of conductive pillars may be reduced, and the risk of manufacturing errors may be lowered.

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