Pseudo static memory device
Abstract:
A pseudo static memory device includes multiple memories, an arbiter and a controller. The memories respectively generate multiple self-refresh request signals. Each of the self-refresh request signals indicates a time period for performing self-refresh operation of corresponding memory. The arbiter receives the self-refresh request signals and generates a latency synchronize flag during the memories being enabled. The controller decides an accessing latency for accessing the memories during an accessing operation according to the latency synchronize flag.
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