Invention Grant
- Patent Title: Field effect transistors with reduced electric field by thickening dielectric on the drain side
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Application No.: US16651294Application Date: 2017-12-27
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Publication No.: US11362188B2Publication Date: 2022-06-14
- Inventor: Dipanjan Basu , Sean T. Ma , Willy Rachmady , Jack T. Kavalieros
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Essential Patents Group, LLP
- International Application: PCT/US2017/068558 WO 20171227
- International Announcement: WO2019/132887 WO 20190704
- Main IPC: H01L29/423
- IPC: H01L29/423 ; H01L29/51 ; H01L29/66 ; H01L29/78

Abstract:
An apparatus is provided which comprises: a source and a drain with a channel region therebetween, the channel region comprising a semiconductor material, and a gate dielectric layer over at least a portion of the channel region, wherein the gate dielectric layer comprises a first thickness proximate to the source and a second thickness proximate to the drain, wherein the second thickness is greater than the first thickness, and wherein at least a portion of the gate dielectric layer comprises a linearly varying thickness over the channel region. Other embodiments are also disclosed and claimed.
Public/Granted literature
- US20200279931A1 REDUCED ELECTRIC FIELD BY THICKENING DIELECTRIC ON THE DRAIN SIDE Public/Granted day:2020-09-03
Information query
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