Invention Grant
- Patent Title: High bandwidth connection between processor dies
-
Application No.: US17205905Application Date: 2021-03-18
-
Publication No.: US11409571B2Publication Date: 2022-08-09
- Inventor: Altug Koker , Abhishek R. Appu , Kiran C. Veernapu , Joydeep Ray , Balaji Vembu
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Jaffery Watson Mendonsa & Hamilton LLP
- Main IPC: G06F9/50
- IPC: G06F9/50 ; G06T1/20

Abstract:
Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive a completion acknowledgment from the plurality of graphics processing units and in response to a determination that the workload is finished, to terminate one or more communication connections on the interconnect bridge. Other embodiments are also disclosed and claimed.
Public/Granted literature
- US20210279104A1 HIGH BANDWIDTH CONNECTION BETWEEN PROCESSOR DIES Public/Granted day:2021-09-09
Information query