Invention Grant
- Patent Title: Physical layer low-latency forward error correction
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Application No.: US17071843Application Date: 2020-10-15
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Publication No.: US11424859B2Publication Date: 2022-08-23
- Inventor: Christopher Michael Brueggen , James Donald Regan , Elene Chobanyan
- Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
- Applicant Address: US TX Houston
- Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
- Current Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
- Current Assignee Address: US TX Houston
- Agency: Sheppard Mullin Richter & Hampton LLP
- Main IPC: H04L1/00
- IPC: H04L1/00 ; H03M13/09 ; H03M13/11

Abstract:
Systems and methods are provided for implementing forward error correction (FEC) on data transferred on a data link on the physical layer. Binary encoding can be done in accordance with a physical unit (phit) FEC format. The phit FEC format allows for correction of two bit errors and comprises a codeword having a variable bit size. Pre-coding the phit enables burst errors associated with the link to converted into bit errors. The data can be transmitted in the phit FEC format to a receiving PHY. The correctable two bit errors at one or more locations within the phit FEC format can then be corrected by decoding at the receiving PHY in accordance with the phit FEC. The FEC techniques can minimize latency in the PHY.
Public/Granted literature
- US20220123860A1 PHYSICAL LAYER LOW-LATENCY FORWARD ERROR CORRECTION Public/Granted day:2022-04-21
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