Invention Grant
- Patent Title: SRAM layout scheme for improving write margin
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Application No.: US16830983Application Date: 2020-03-26
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Publication No.: US11430796B2Publication Date: 2022-08-30
- Inventor: Junichi Hirotsu , Daiki Ito
- Applicant: Winbond Electronics Corp.
- Applicant Address: TW Taichung
- Assignee: Winbond Electronics Corp.
- Current Assignee: Winbond Electronics Corp.
- Current Assignee Address: TW Taichung
- Agency: Birch, Stewart, Kolasch & Birch, LLP
- Priority: JPJP2019-071739 20190404
- Main IPC: G11C5/02
- IPC: G11C5/02 ; H01L27/11 ; G11C11/412 ; G11C5/06 ; G11C11/419 ; G11C5/14 ; H01L27/02

Abstract:
A semiconductor device is provided. The semiconductor can apply different voltages to sources and bases (bulks, N-type well) of pull-up transistors and improves write margin of memory cells. An SRAM of the invention includes P-well regions PW_1 and PW_2, an N-well region NW, a first metal wire M1, and a second metal wire M2. The P-well regions PW_1 and PW_2 extend in a first direction, and pull-down transistors and accessing transistors are formed therein. The N-well region NW extends in first direction, and pull-up transistors are formed therein. The first metal wire M1 extends in the first direction on the N-well region NW and is electrically connected to the N-well region NW. The second metal wire M2 extends in a second direction orthogonal to the first direction and electrically connected to a common S/D region of a pair of pull-up transistors that are formed in the N-well region NW.
Public/Granted literature
- US20200321343A1 SEMICONDUCTOR DEVICE Public/Granted day:2020-10-08
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