Invention Grant
- Patent Title: Semiconductor package structure with landing pads and manufacturing method thereof
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Application No.: US16886782Application Date: 2020-05-29
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Publication No.: US11437336B2Publication Date: 2022-09-06
- Inventor: Jeffrey Wang , Jen-I Huang , Kun-Yung Huang
- Applicant: Powertech Technology Inc.
- Applicant Address: TW Hsinchu County
- Assignee: Powertech Technology Inc.
- Current Assignee: Powertech Technology Inc.
- Current Assignee Address: TW Hsinchu County
- Agency: JCIPRNET
- Priority: TW109114563 20200430
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/31 ; H01L21/48 ; H01L21/56

Abstract:
A semiconductor package structure includes a first redistribution layer, a plurality of conductive connectors, a chip, and an encapsulant. The first redistribution layer has a first surface and a second surface opposite to the first surface. The first redistribution layer includes at least one conductive pattern and at least one dielectric layer stacked on each other. The conductive pattern includes a plurality of landing pads, and each of the landing pads is separated from the dielectric layer. The conductive connectors are located on the first surface. Each of the conductive connectors is corresponding to and electrically connected to one of the landing pads. The chip is located on the first surface. The chip is electrically connected to the first redistribution layer. The encapsulant encapsulates the chip and the conductive connectors. A manufacturing method of a semiconductor package structure is also provided.
Public/Granted literature
- US20210343674A1 SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF Public/Granted day:2021-11-04
Information query
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