Invention Grant
- Patent Title: Large panel displays with reduced routing line resistance
-
Application No.: US17143939Application Date: 2021-01-07
-
Publication No.: US11462608B2Publication Date: 2022-10-04
- Inventor: Shinya Ono , Chin-Wei Lin , Akira Matsudaira , Jiun-Jye Chang , Jung Yen Huang , Pei-En Chang , Rungrot Kitsomboonloha , Szu-Hsien Lee
- Applicant: Apple Inc.
- Applicant Address: US CA Cupertino
- Assignee: Apple Inc.
- Current Assignee: Apple Inc.
- Current Assignee Address: US CA Cupertino
- Agency: Treyz Law Group, P.C.
- Agent Jason Tsai
- Main IPC: G09G3/3225
- IPC: G09G3/3225 ; G09G3/3266 ; H01L27/32 ; H01L29/786 ; H01L27/12 ; H01L29/49

Abstract:
An electronic device may include a display with pixels formed using light-emitting diodes, thin-film silicon transistors, thin-film semiconducting-oxide transistors, and capacitors. The silicon transistors, semiconducting-transistors, and capacitors may have control terminals that are coupled to gate or routing lines that extend across the face of the display and that are formed in a low resistance source-drain metal routing layer. Forming routing/gate lines using the low resistance source-drain metal routing layer dramatically reduces the resistance of the gate lines, which enables better timing margins for large display panels operating at higher refresh rates.
Public/Granted literature
- US20210305353A1 Large Panel Displays with Reduced Routing Line Resistance Public/Granted day:2021-09-30
Information query
IPC分类: