Invention Grant
- Patent Title: 3D IC method and device
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Application No.: US17315166Application Date: 2021-05-07
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Publication No.: US11515202B2Publication Date: 2022-11-29
- Inventor: Paul M. Enquist , Gaius Gillman Fountain, Jr. , Qin-Yi Tong
- Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Applicant Address: US CA San Jose
- Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Current Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Current Assignee Address: US CA San Jose
- Agency: Knobbe, Martens, Olson & Bear, LLP
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L21/768 ; H01L23/48 ; H01L25/065 ; H01L25/00 ; H01L27/06

Abstract:
A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface.
Public/Granted literature
- US20210313225A1 3D IC METHOD AND DEVICE Public/Granted day:2021-10-07
Information query
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