Invention Grant
- Patent Title: Vertical fin field effect transistor with a reduced gate-to-bottom source/drain parasitic capacitance
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Application No.: US16685022Application Date: 2019-11-15
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Publication No.: US11515401B2Publication Date: 2022-11-29
- Inventor: Chen Zhang , Kangguo Cheng , Xin Miao , Wenyu Xu
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Tutunjian & Bitetto, P.C.
- Agent Randy Emilio Tejeda
- Main IPC: H01L21/82
- IPC: H01L21/82 ; H01L29/66 ; H01L29/78 ; H01L29/10 ; H01L21/8234 ; H01L29/06 ; H01L29/786 ; H01L29/423
Abstract:
A method of forming a vertical fin field effect device is provided. The method includes, forming a vertical fin on a substrate, forming a masking block on the vertical fin, wherein the masking block extends a distance outward from the vertical fin sidewalls and endwalls, and a portion of the substrate surrounding the masking block is exposed. The method further includes removing at least a portion of the exposed portion of the substrate to form a recess and a fin mesa below the vertical fin, removing a portion of the fin mesa to form an undercut recess below an overhanging portion of the masking block, forming a spacer layer on the masking block and in the undercut recess, and removing a portion of the spacer layer to form an undercut spacer in the undercut recess.
Public/Granted literature
- US20200083353A1 VERTICAL FIN FIELD EFFECT TRANSISTOR WITH A REDUCED GATE-TO-BOTTOM SOURCE/DRAIN PARASITIC CAPACITANCE Public/Granted day:2020-03-12
Information query
IPC分类:
