Invention Grant
- Patent Title: Memory management to improve power performance
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Application No.: US17116991Application Date: 2020-12-09
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Publication No.: US11520498B2Publication Date: 2022-12-06
- Inventor: Nadav Bonen , Sridhar Muthrasanallur , Srinivas Pandruvada , Vishwanath Somayaji , Prashant Kodali
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Priority: IN202041026926 20200625
- Main IPC: G06F3/06
- IPC: G06F3/06

Abstract:
Logical memory is divided into two regions. Data in the first region is always retained. The first region of memory is designated online (or powered on) and is not offlined during standby or low power mode. The second region is the rest of the memory which can be potentially placed in non-self-refresh mode during standby by offlining the memory region. Content in the second region can be moved to the first region or can be flushed to another memory managed by the operating system. When the first region does not have enough space to accommodate data from the second region, the operating system can increase the logical size of the first region. Retaining the content of the first region by putting that region in self-refresh and saving power in the second region by not putting it in self-refresh is performed by an improved Partial Array Self Refresh scheme.
Public/Granted literature
- US20210405892A1 MEMORY MANAGEMENT TO IMPROVE POWER PERFORMANCE Public/Granted day:2021-12-30
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