- Patent Title: Semiconductor package structure and manufacturing method thereof
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Application No.: US16856011Application Date: 2020-04-22
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Publication No.: US11522000B2Publication Date: 2022-12-06
- Inventor: Hung-Hsin Hsu , Wen-Hsiung Chang
- Applicant: Powertech Technology Inc.
- Applicant Address: TW Hsinchu County
- Assignee: Powertech Technology Inc.
- Current Assignee: Powertech Technology Inc.
- Current Assignee Address: TW Hsinchu County
- Agency: JCIPRNET
- Priority: TW108135048 20190927
- Main IPC: H01L27/14
- IPC: H01L27/14 ; H01L27/146

Abstract:
A semiconductor package structure including a sensor die, a substrate, a light blocking layer, a circuit layer, a dam structure and an underfill is provided. The sensor die has a sensing surface. The sensing surface includes an image sensing area and a plurality of conductive bumps. The substrate is disposed on the sensing surface. The light blocking layer is located between the substrate and the sensor die. The circuit layer is disposed on the light blocking layer. The sensor die is electrically connected to the circuit layer by the conductive bumps. The dam structure is disposed on the substrate and surrounds the image sensing area. Opposite ends of the dam structure directly contact the sensor die and the light blocking layer. The underfill is disposed between the dam structure and the conductive bumps.
Public/Granted literature
- US20210098517A1 SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF Public/Granted day:2021-04-01
Information query
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