Invention Grant
- Patent Title: CMOS compatible isolation leakage improvements in gallium nitride transistors
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Application No.: US16000714Application Date: 2018-06-05
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Publication No.: US11527610B2Publication Date: 2022-12-13
- Inventor: Marko Radosavljevic , Sansaptak Dasgupta , Han Wui Then
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L29/20 ; H01L27/088 ; H01L29/08 ; H01L29/66 ; H01L21/02 ; H01L21/762 ; H01L21/3105 ; H01L21/306 ; H01L27/06 ; H01L29/205 ; H01L21/8252 ; H01L29/778
Abstract:
An integrated circuit structure comprises a silicon substrate and a III-nitride (III-N) substrate over the silicon substrate. A first III-N transistor and a second III-N transistor is on the III-N substrate. An insulator structure is formed in the III-N substrate between the first III-N transistor and the second III-N, wherein the insulator structure comprises one of: a shallow trench filled with an oxide, nitride or low-K dielectric; or a first gap adjacent to the first III-N transistor and a second gap adjacent to the second III-N transistor.
Information query
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