Invention Grant
- Patent Title: Managing error-handling flows in memory devices
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Application No.: US17205091Application Date: 2021-03-18
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Publication No.: US11532373B2Publication Date: 2022-12-20
- Inventor: Kishore Kumar Muchherla , Shane Nowell , Mustafa N. Kaynak , Sampath K. Ratnam , Peter Feeley , Sivagnanam Parthasarathy , Devin M. Batutis , Xiangang Luo
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Lowenstein Sandler LLP
- Main IPC: G11C29/42
- IPC: G11C29/42 ; G11C16/26 ; G11C29/44 ; G11C16/10 ; G11C29/12

Abstract:
Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including detecting a read error with respect to data residing in a block of the memory device, wherein the block is associated with a voltage offset bin, determining an order of a plurality of error-handling operations to be performed to recovery data associated with the read error, wherein the order is specified in a metadata table and is based on the voltage offset bin associated with the block, and performing at least one error-handling operation of the plurality of error-handling operations in the order specified by the metadata table.
Public/Granted literature
- US20220301652A1 MANAGING ERROR-HANDLING FLOWS IN MEMORY DEVICES Public/Granted day:2022-09-22
Information query