公开(公告)号：US20250147686A1

公开(公告)日：2025-05-08

申请号：US19017960

申请日：2025-01-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sampath K. Ratnam ,  Vamsi Pavan Rayaprolu ,  Mustafa N. Kaynak ,  Sivagnanam Parthasarathy ,  Kishore Kumar Muchherla ,  Shane Nowell ,  Peter Feeley ,  Qisong Lin

IPC: G06F3/06 ,  G06F11/10 ,  G06F11/14 ,  G11C29/52

Abstract: An example system includes a memory device; and a processing device, operatively coupled to the memory device, to perform operations, including: programming a plurality of pages of the memory device; adjusting a program verify voltage associated with the plurality of pages; responsive to determining that a first error rate of a first page of the plurality of pages exceeds a second error rate of a second page of the plurality of pages, performing a recovery operation on the first page to produce recovered data; and storing the recovered data on the memory device.

公开(公告)号：US11928347B2

公开(公告)日：2024-03-12

申请号：US18114967

申请日：2023-02-27

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Mustafa N Kaynak ,  Peter Feeley ,  Sampath K Ratnam ,  Shane Nowell ,  Sivagnanam Parthasarathy ,  Karl D Schuh ,  Jiangang Wu

IPC: G06F3/06 ,  G11C16/26

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0679 ,  G11C16/26

Abstract: A processing device of a memory sub-system is configured to sort a plurality of blocks of the memory device; identify, based on scanning of a first block at a first location of the plurality of sorted block, a first voltage bin associated with the first block; identify, based on scanning of a second block at a second location of the plurality of sorted blocks, a second voltage bin associated with the second block; and responsive to determining that the first voltage bin matches the second voltage bin, assign the first voltage bin to each block that is located between the first location of the plurality of sorted blocks and the second location of the plurality of sorted blocks.

公开(公告)号：US11841753B2

公开(公告)日：2023-12-12

申请号：US17466499

申请日：2021-09-03

Applicant: Micron Technology, Inc.

Inventor： Shane Nowell ,  Sivagnanam Parthasarathy

IPC: G06F11/30 ,  G06F1/20 ,  G01K3/00 ,  G11C11/56

CPC classification number: G06F1/206 ,  G01K3/005 ,  G06F1/203 ,  G11C11/5635

Abstract: An operating temperature of a memory sub-system is identified. It is determined whether the operating temperature satisfies a first temperature condition associated with a threshold temperature. Upon determining that the operating temperature satisfies the first temperature condition, one or more operations are performed on at least one data block at a memory component of the memory sub-system until the operating temperature changes to satisfy a second temperature condition associated with the threshold temperature. The one or more operations are selected to be performed based on a difference between the operating temperature and the threshold temperature.

公开(公告)号：US11837291B2

公开(公告)日：2023-12-05

申请号：US17589491

申请日：2022-01-31

Applicant: Micron Technology, Inc.

Inventor： Vamsi Pavan Rayaprolu ,  Mustafa N. Kaynak ,  Michael Sheperek ,  Larry J. Koudele ,  Shane Nowell

IPC: G11C16/10 ,  G06F12/06 ,  G11C16/08

CPC classification number: G11C16/107 ,  G06F12/06 ,  G11C16/08

Abstract: One or more data units at a memory device and that are associated with one or more dice of a die group comprising a plurality of dice are programmed. A voltage offset bin associated with the plurality of dice in the die group is determined based on a subset of dice of the die group.

公开(公告)号：US20230282293A1

公开(公告)日：2023-09-07

申请号：US18110008

申请日：2023-02-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kishore Kumar Muchherla ,  Mustafa N Kaynak ,  Sampath K Ratnam ,  Shane Nowell ,  Peter Feeley ,  Sivagnanam Parthasarathy

IPC: G11C16/34 ,  G11C16/30 ,  G11C16/10 ,  G11C16/32 ,  G11C16/26

CPC classification number: G11C16/3404 ,  G11C16/30 ,  G11C16/102 ,  G11C16/32 ,  G11C16/26

Abstract: A processing device of a memory sub-system is configured to identify a read level of a plurality of read levels associated with a voltage bin of a plurality of voltage bins of a memory device; assign a first threshold voltage offset to the read level of the voltage bin; assign a second threshold voltage offset to the read level of the voltage bin; perform, on block associated with the read level, a first operation of a first operation type using the first threshold voltage offset; and perform, on the blocks associated with the read level, a second operation of a second operation type using the second threshold voltage offset.

公开(公告)号：US11710527B2

公开(公告)日：2023-07-25

申请号：US17868685

申请日：2022-07-19

Applicant: Micron Technology, Inc.

Inventor： Vamsi Pavan Rayaprolu ,  Kishore Kumar Muchherla ,  Peter Feeley ,  Sampath K. Ratnam ,  Sivagnanam Parthasarathy ,  Qisong Lin ,  Shane Nowell ,  Mustafa N. Kaynak

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/14 ,  G11C29/00 ,  G06F11/07 ,  G11C16/26 ,  G06F3/06 ,  G11C16/04

CPC classification number: G11C16/34 ,  G06F3/0619 ,  G06F3/0634 ,  G06F3/0679 ,  G06F11/073 ,  G06F11/076 ,  G06F11/079 ,  G06F11/0793 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3445 ,  G11C16/3459 ,  G11C29/00 ,  G11C29/84 ,  G11C16/0483 ,  G11C2207/229 ,  G11C2207/2272 ,  G11C2207/2281

Abstract: A determination that a first programming operation has been performed on a particular memory cell can be made. A determination can be made, based on one or more threshold criteria, whether the particular memory cell has transitioned from a state associated with a decreased error rate to another state associated with an increased error rate. In response to determining that the particular memory cell has transitioned from the state associated with the decreased error rate to the another state associated with the increased error rate, an operation can be performed on the particular memory cell to transition the particular memory cell from the another state associated with the increased error rate to the state associated with the decreased error rate.

公开(公告)号：US11662786B2

公开(公告)日：2023-05-30

申请号：US17447167

申请日：2021-09-08

Applicant: Micron Technology, Inc.

Inventor： Shane Nowell ,  Sampath K. Ratnam ,  Vamsi Pavan Rayaprolu

IPC: G11C11/06 ,  G06F1/20 ,  G06F1/3234 ,  G11C11/56

CPC classification number: G06F1/206 ,  G06F1/3275 ,  G11C11/5628

Abstract: A processing device in a memory sub-system stores data at a first voltage level in a memory cell in a first segment of the memory sub-system, and determines a temperature change between a current temperature associated with the memory cell and a new temperature. The processing device further determines a voltage level read from the memory cell at the new temperature, determines a difference between the voltage level read from the memory cell and the first voltage level, and determines a temperature compensation value based on the difference between the voltage level read from the memory cell and the first voltage level in view of the temperature change.

公开(公告)号：US11625177B2

公开(公告)日：2023-04-11

申请号：US17100709

申请日：2020-11-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shane Nowell ,  Michael Sheperek ,  Larry J. Koudele ,  Vamsi Pavan Rayaprolu

IPC: G06F12/00 ,  G06F3/06

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to initiate a scan process on a plurality of block families of the memory device; responsive to determining, based on the scan process, that a first block family of the plurality of block families and a second block family of the plurality of block families meet a combining criterion, merge the first block family and the second block family; and responsive to determining that a terminating condition has been satisfied, terminate the scan process.

公开(公告)号：US11587627B2

公开(公告)日：2023-02-21

申请号：US17233320

申请日：2021-04-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kishore Kumar Muchherla ,  Mustafa N Kaynak ,  Sampath K Ratnam ,  Shane Nowell ,  Peter Feeley ,  Sivagnanam Parthasarathy

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/30 ,  G11C16/10 ,  G11C16/32 ,  G11C16/26

Abstract: A processing device of a memory sub-system is configured to identify a read level of a plurality of read levels associated with a voltage bin of a plurality of voltage bins of a memory device; assign a first threshold voltage offset to the read level of the voltage bin; assign a second threshold voltage offset to the read level of the voltage bin; perform, on block associated with the read level, a first operation of a first operation type using the first threshold voltage offset; and perform, on the blocks associated with the read level, a second operation of a second operation type using the second threshold voltage offset.

公开(公告)号：US20220366997A1

公开(公告)日：2022-11-17

申请号：US17877810

申请日：2022-07-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vamsi Pavan Rayaprolu ,  Shane Nowell ,  Michael Sheperek ,  Steven Michael Kientz

IPC: G11C29/44 ,  G11C29/42 ,  G11C29/12 ,  G11C29/10 ,  G11C16/34

Abstract: A system can include a memory device and a processing device to perform operations that include determining a calibration scan frequency based on an amount of elapsed time since a previous write operation performed on the memory device, determining, based on the calibration scan frequency, whether one or more scan criteria are satisfied, responsive to determining that the one or more scan criteria are satisfied, identifying one or more block families, and calibrating one or more bin pointers of each of the identified block families, wherein the calibrating comprises: for each of the identified block families, updating each of the one or more bin pointers of the identified block family based on a data state metric of at least one block of the identified block family.