Invention Grant
- Patent Title: Transistors on heterogeneous bonding layers
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Application No.: US16222946Application Date: 2018-12-17
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Publication No.: US11532719B2Publication Date: 2022-12-20
- Inventor: Kimin Jun , Jack T. Kavalieros , Gilbert Dewey , Willy Rachmady , Aaron Lilak , Brennen Mueller , Hui Jae Yoo , Patrick Morrow , Anh Phan , Cheng-Ying Huang , Ehren Mannebach
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L29/423
- IPC: H01L29/423 ; H01L29/66 ; H01L29/49 ; H01L29/45 ; H01L29/786 ; H01L21/762 ; H01L21/02 ; H01L29/06

Abstract:
Embodiments herein describe techniques for a semiconductor device over a semiconductor substrate. A first bonding layer is above the semiconductor substrate. One or more nanowires are formed above the first bonding layer to be a channel layer. A gate electrode is around a nanowire, where the gate electrode is in contact with the first bonding layer and separated from the nanowire by a gate dielectric layer. A source electrode or a drain electrode is in contact with the nanowire, above a bonding area of a second bonding layer, and separated from the gate electrode by a spacer, where the second bonding layer is above and in direct contact with the first bonding layer.
Information query
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