Invention Grant
- Patent Title: Stacked semiconductor package and method of forming the same
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Application No.: US16987440Application Date: 2020-08-07
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Publication No.: US11562963B2Publication Date: 2023-01-24
- Inventor: Chin Lee Kuan , Bok Eng Cheah , Jackson Chung Peng Kong , Sameer Shekhar , Amit Jain
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Viering, Jentschura & Partner mbB
- Priority: MYPI2020002905 20200605
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L23/00 ; H01L21/48

Abstract:
According to various examples, a stacked semiconductor package is described. The stacked semiconductor package may include a package substrate. The stacked semiconductor package may also include a base die disposed on and electrically coupled to the package substrate. The stacked semiconductor package may further include a mold portion disposed on the package substrate at a periphery of the base die, the mold portion may include a through-mold interconnect electrically coupled to the package substrate. The stacked semiconductor package may further include a semiconductor device having a first section disposed on the base die and a second section disposed on the mold portion, wherein the second section of the semiconductor device may be electrically coupled to the package substrate through the through-mold interconnect.
Public/Granted literature
- US20210384135A1 STACKED SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME Public/Granted day:2021-12-09
Information query
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