Invention Grant
- Patent Title: Method of planarizing insulating layer for memory device
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Application No.: US16850591Application Date: 2020-04-16
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Publication No.: US11587941B2Publication Date: 2023-02-21
- Inventor: Byung Woo Kang , Sae Jun Kwon , Hwal Pyo Kim , Jin Taek Park , Yang Seok Lim , Young Ock Hong
- Applicant: SK hynix Inc.
- Applicant Address: KR Icheon-si
- Assignee: SK hynix Inc.
- Current Assignee: SK hynix Inc.
- Current Assignee Address: KR Icheon-si
- Agency: William Park & Associates Ltd.
- Priority: KRKR10-2019-0101738 20190820
- Main IPC: H01L27/11556
- IPC: H01L27/11556 ; H01L27/11582 ; H01L21/822 ; H01L21/762 ; H01L21/8234

Abstract:
A method of manufacturing a semiconductor device includes forming a stacked structure including trenches having different depths, forming an insulating layer on the stacked structure to fill the trenches, and forming a plurality of protrusions located corresponding to locations of the trenches by patterning the insulating layer. The method also includes forming insulating patterns filling the trenches, respectively, by planarizing the patterned insulating layer including the plurality of protrusions.
Public/Granted literature
- US20210057431A1 MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE Public/Granted day:2021-02-25
Information query
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