Invention Grant
- Patent Title: Stacked connections in 3D memory and methods of making the same
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Application No.: US17112448Application Date: 2020-12-04
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Publication No.: US11600636B2Publication Date: 2023-03-07
- Inventor: Jun Liu , Zongliang Huo
- Applicant: Yangtze Memory Technologies Co., Ltd.
- Applicant Address: CN Hubei
- Assignee: Yangtze Memory Technologies Co., Ltd.
- Current Assignee: Yangtze Memory Technologies Co., Ltd.
- Current Assignee Address: CN Hubei
- Agency: Sterne, Kessler, Goldstein & Fox P.L.L.C.
- Main IPC: H01L27/11582
- IPC: H01L27/11582 ; H01L21/02 ; H01L21/225 ; H01L21/306 ; H01L21/311 ; H01L27/1157 ; H01L29/10 ; H01L21/28 ; H01L21/3105 ; H01L21/321

Abstract:
Embodiments of three-dimensional memory device architectures and fabrication methods therefore are disclosed. In an example, the memory device includes a substrate having a first layer stack on it. The first layer stack includes alternating conductor and insulator layers. A second layer stack is disposed over the first layer stack where the second layer stack also includes alternating conductor and insulator layers. One or more vertical structures extend through the first layers stack. A conductive material is disposed on a top surface of the one or more vertical structures. One or more second vertical structures extend through the second layer stack and through a portion of the conductive material.
Public/Granted literature
- US20210091115A1 STACKED CONNECTIONS IN 3D MEMORY AND METHODS OF MAKING THE SAME Public/Granted day:2021-03-25
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