Invention Grant
- Patent Title: Arsenic-doped epitaxial, source/drain regions for NMOS
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Application No.: US16145375Application Date: 2018-09-28
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Publication No.: US11610889B2Publication Date: 2023-03-21
- Inventor: Anand Murthy , Ryan Keech , Nicholas G. Minutillo , Ritesh Jhaveri
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L29/66 ; H01L29/51 ; H01L29/78 ; H01L29/08 ; H01L29/49 ; H01L29/167 ; H01L21/8238 ; H01L29/06 ; H01L29/10

Abstract:
Techniques are disclosed for providing an integrated circuit structure having NMOS transistors including an arsenic-doped interface layer between epitaxially grown source/drain regions and a channel region. The arsenic-doped interface layer may include, for example, arsenic-doped silicon (Si:As) having arsenic concentrations in a range of about 1E20 atoms per cm3 to about 5E21 atoms per cm3. The interface layer may have a relatively uniform thickness in a range of about 0.5 nm to full fill where the entire source/drain region is composed of the Si:As. In cases where the arsenic-doped interface layer only partially fills the source/drain regions, another n-type doped semiconductor material can fill remainder (e.g., phosphorus-doped III-V compound or silicon). The use of a layer having a high arsenic concentration can provide improved NMOS performance in the form of abrupt junctions in the source/drain regions and highly conductive source/drain regions with negligible diffusion of arsenic into the channel region.
Information query
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