Invention Grant
- Patent Title: Translation lookaside buffer to implement adapative page size
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Application No.: US16973998Application Date: 2018-09-28
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Publication No.: US11615034B2Publication Date: 2023-03-28
- Inventor: Zhaojuan Bian , Kebing Wang
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Jaffery Watson Mendonsa & Hamilton LLP
- International Application: PCT/CN2018/108215 WO 20180928
- International Announcement: WO2020/061992 WO 20200402
- Main IPC: G06F12/10
- IPC: G06F12/10 ; G06F12/1045 ; G06F12/02 ; G06F12/06 ; G06F12/0871 ; G06F12/0882

Abstract:
Embodiments described herein provide an apparatus comprising a processor to reserve a block of physical memory communicatively coupled to a processor, allocate a first portion of the block of physical memory for use with one or more processes executing on the processor, the first portion configured as a single memory page having a first page size, and in response to a determination that an amount of physical memory required by the one or more processes executing on the processor exceeds a first threshold allocate additional memory to the first portion of the block of physical memory, and increase the single memory page from a first page size to a second page size. Other embodiments may be described and claimed.
Public/Granted literature
- US20210248085A1 TRANSLATION LOOKASIDE BUFFER TO IMPLEMENT ADAPATIVE PAGE SIZE Public/Granted day:2021-08-12
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