Invention Grant
- Patent Title: Enhancement mode startup circuit with JFET emulation
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Application No.: US17314523Application Date: 2021-05-07
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Publication No.: US11621708B2Publication Date: 2023-04-04
- Inventor: Michael Lueders , Johan Strydom , Cetin Kaya , Maik Peter Kaufmann
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Frank D. Cimino
- Main IPC: H02M1/08
- IPC: H02M1/08 ; H03K17/22 ; H02M1/36 ; H02M3/335 ; H02M1/00

Abstract:
A startup circuit adapted to be coupled to an input voltage supply and operable to supply an output voltage at an output terminal, the startup circuit including: a first transistor having a first control terminal, a first current terminal and a second current terminal, the first current terminal adapted to be coupled to the input voltage supply and the second current terminal coupled to the output terminal; a precharge circuit having a first terminal, a second terminal and a third terminal, the second terminal adapted to be coupled to the input voltage supply and the third terminal coupled to the first control terminal; a current limiter coupled to the precharge circuit, the first control terminal and the second current terminal; a second transistor having a second control terminal, a third current terminal and a fourth current terminal, the third current terminal coupled to the precharge circuit and the second control terminal adapted to be coupled to a control signal; and a third transistor having a third control terminal, a fifth current terminal and a sixth current terminal, the fifth current terminal coupled to the first control terminal and the third control terminal is adapted to be coupled to the control signal.
Public/Granted literature
- US20210265992A1 ENHANCEMENT MODE STARTUP CIRCUIT WITH JFET EMULATION Public/Granted day:2021-08-26
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