Invention Grant
- Patent Title: Wall for isolation enhancement
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Application No.: US17366836Application Date: 2021-07-02
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Publication No.: US11632856B2Publication Date: 2023-04-18
- Inventor: Andrew Southworth , Kevin Wilder , James Benedict , Mary K. Herndon , Thomas V. Sikina , John P. Haven
- Applicant: RAYTHEON COMPANY
- Applicant Address: US MA Waltham
- Assignee: RAYTHEON COMPANY
- Current Assignee: RAYTHEON COMPANY
- Current Assignee Address: US MA Waltham
- Agency: Cantor Colburn LLP
- Main IPC: H05K1/02
- IPC: H05K1/02 ; H05K1/11 ; H05K1/18 ; H05K3/26 ; H05K3/30 ; H05K5/00 ; H05K5/06 ; H05K9/00 ; H01L23/34 ; H01L23/498 ; H01L23/552 ; H01Q1/38 ; H01Q1/52 ; H05K3/00

Abstract:
A circuit assembly is provided and includes a printed circuit board (PCB) having a circuit element region and defining a trench surrounding an entirety of the circuit element region, a circuit element disposed within the circuit element region of the PCB; and a Faraday wall. The Faraday wall includes a solid, unitary body having a same shape as the trench. The Faraday wall is disposed within the trench to surround an entirety of the circuit element.
Public/Granted literature
- US20210337651A1 WALL FOR ISOLATION ENHANCEMENT Public/Granted day:2021-10-28
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