Invention Grant
- Patent Title: III-V source/drain in top NMOS transistors for low temperature stacked transistor contacts
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Application No.: US16954126Application Date: 2018-03-28
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Publication No.: US11640961B2Publication Date: 2023-05-02
- Inventor: Gilbert Dewey , Ravi Pillarisetty , Jack T. Kavalieros , Aaron D. Lilak , Willy Rachmady , Rishabh Mehandru , Kimin Jun , Anh Phan , Hui Jae Yoo , Patrick Morrow , Cheng-Ying Huang , Matthew V. Metz
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2018/024936 WO 20180328
- International Announcement: WO2019/190508 WO 20191003
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L21/822 ; H01L21/8238 ; H01L29/78 ; H01L27/06 ; H01L29/06 ; H01L29/08 ; H01L29/66
Abstract:
An integrated circuit structure comprises a lower device layer that includes a first structure comprising a plurality of PMOS transistors. An upper device layer is formed on the lower device layer, wherein the upper device layer includes a second structure comprising a plurality of NMOS transistors having a group III-V material source/drain region.
Public/Granted literature
- US20210057413A1 III-V SOURCE/DRAIN IN TOP NMOS TRANSISTORS FOR LOW TEMPERATURE STACKED TRANSISTOR CONTACTS Public/Granted day:2021-02-25
Information query
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