Invention Grant
- Patent Title: Shared memory mesh for switching
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Application No.: US16549915Application Date: 2019-08-23
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Publication No.: US11641326B2Publication Date: 2023-05-02
- Inventor: Karl S. Papadantonakis , Robert Southworth , Arvind Srinivasan , Helia A. Naeimi , James E. McCormick, Jr. , Jonathan Dama , Ramakrishna Huggahalli , Roberto Penaranda Cebrian
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Compass IP Law PC
- Main IPC: H04L49/103
- IPC: H04L49/103 ; H04L47/625 ; H04L47/6275 ; H04L49/00 ; H04L67/101 ; H04L7/10 ; H04L67/10

Abstract:
Examples are described herein that relate to a mesh in a switch fabric. The mesh can include one or more buses that permit operations (e.g., read, write, or responses) to continue in the same direction, drop off to a memory, drop off a bus to permit another operation to use the bus, or receive operations that are changing direction. A latency estimate can be determined at least for operations that drop off from a bus to permit another operation to use the bus or receive and channel operations that are changing direction. An operation with a highest latency estimate (e.g., time of traversing a mesh) can be permitted to use the bus, even causing another operation, that is not to change direction, to drop off the bus and re-enter later.
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