公开(公告)号：US11038815B2

公开(公告)日：2021-06-15

申请号：US16451454

申请日：2019-06-25

Applicant: Intel Corporation

Inventor： Mrittika Ganguli ,  Anjaneya Reddy Chagam Reddy ,  Francesc Guim Bernat ,  Arvind Srinivasan

IPC: H04L12/911 ,  H04L12/917 ,  H04L12/24 ,  H04L29/08 ,  H04L12/873 ,  H04L12/875

Abstract: Technologies for managing burst bandwidth requirements are disclosed. In the illustrative embodiment, a software-defined network (SDN) controller monitors storage devices in a data center. If a storage device fails, the SDN controller manages the bandwidth used to replicate the data that was stored on the failed storage device. The SDN controller may allocate an initial amount of bandwidth based on one or more parameters of the storage device, and the SDN controller may increase the bandwidth in a series of discrete steps. In another embodiment, the SDN controller may predict a bandwidth burst based on sequential writes at a storage sled from several compute devices, and allocate bandwidth accordingly in a tiered manner.

公开(公告)号：US11641326B2

公开(公告)日：2023-05-02

申请号：US16549915

申请日：2019-08-23

Applicant: Intel Corporation

Inventor： Karl S. Papadantonakis ,  Robert Southworth ,  Arvind Srinivasan ,  Helia A. Naeimi ,  James E. McCormick, Jr. ,  Jonathan Dama ,  Ramakrishna Huggahalli ,  Roberto Penaranda Cebrian

IPC: H04L49/103 ,  H04L47/625 ,  H04L47/6275 ,  H04L49/00 ,  H04L67/101 ,  H04L7/10 ,  H04L67/10

Abstract: Examples are described herein that relate to a mesh in a switch fabric. The mesh can include one or more buses that permit operations (e.g., read, write, or responses) to continue in the same direction, drop off to a memory, drop off a bus to permit another operation to use the bus, or receive operations that are changing direction. A latency estimate can be determined at least for operations that drop off from a bus to permit another operation to use the bus or receive and channel operations that are changing direction. An operation with a highest latency estimate (e.g., time of traversing a mesh) can be permitted to use the bus, even causing another operation, that is not to change direction, to drop off the bus and re-enter later.

公开(公告)号：US20190042741A1

公开(公告)日：2019-02-07

申请号：US16142693

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Akeem Abodunrin ,  Lev Faerman ,  Scott Dubal ,  Suyog Kulkarni ,  Anjali Singhai Jain ,  Eliel Louzoun ,  Nrupal Jani ,  Yadong Li ,  Eliezer Tamir ,  Arvind Srinivasan ,  Ben-Zion Friedman

IPC: G06F21/55 ,  G06F13/40

Abstract: Technologies for control plane separation at a network interface controller (NIC) of a compute device configured to transmit, by a resource of the compute device, commands to a physical function managed by a network interface controller (NIC) of the compute device. The NIC is further to establish a data plane separate from a control plane, wherein the control plane comprises one of the trusted control path and the untrusted control path. Additionally, the resource is configured to transmit the commands via one of the trusted control path or the untrusted control path based on a trust level associated with the physical function. Other embodiments are described herein.

公开(公告)号：US12212502B2

公开(公告)日：2025-01-28

申请号：US17084526

申请日：2020-10-29

Applicant: Intel Corporation

Inventor： Mark Debbage ,  Robert Southworth ,  Arvind Srinivasan ,  Cheolmin Park ,  Todd Rimmer ,  Brian S. Hausauer

IPC: H04L47/34 ,  H04L1/1607 ,  H04L47/125

Abstract: Examples described herein relate to technologies for reliable packet transmission. In some examples, a network interface includes circuitry to: receive a request to transmit a packet to a destination device, select a path for the packet, provide a path identifier identifying one of multiple paths from the network interface to a destination and Path Sequence Number (PSN) for the packet, wherein the PSN is to identify a packet transmission order over the selected path, include the PSN in the packet, and transmit the packet. In some examples, if the packet is a re-transmit of a previously transmitted packet, the circuitry is to: select a path for the re-transmit packet, and set a PSN of the re-transmit packet that is a current packet transmission number for the selected path for the re-transmit packet. In some examples, a network interface includes circuitry to process a received packet to at least determine a Path Sequence Number (PSN) for the received packet, wherein the PSN is to provide an order of packet transmissions for a path associated with the received packet, process a second received packet to at least determine its PSN, and based on the PSN of the second received packet not being a next sequential value after the PSN of the received packet, cause transmission of a re-transmit request to a sender of the packet and the second packet.

公开(公告)号：US11916800B2

公开(公告)日：2024-02-27

申请号：US16912553

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： David Arditti Ilitzky ,  John Greth ,  Robert Southworth ,  Karl S. Papadantonakis ,  Bongjin Jung ,  Arvind Srinivasan

IPC: H04L47/283 ,  H04L43/087 ,  H04L43/16 ,  H04L49/00 ,  H04L47/125 ,  H04L49/25 ,  H04L49/90 ,  H04L47/62

CPC classification number: H04L47/283 ,  H04L43/087 ,  H04L43/16 ,  H04L47/125 ,  H04L47/6205 ,  H04L49/25 ,  H04L49/3063 ,  H04L49/9042

Abstract: Examples describe an egress port manager that uses an adaptive jitter selector to apply a jitter threshold level for a buffer, wherein the jitter threshold level is to indicate when egress of a packet segment from the buffer is allowed, wherein a packet segment comprises a packet header and wherein the jitter threshold level is adaptive based on a switch fabric load. In some examples, the jitter threshold level is to indicate a number of segments for the buffer's head of line (HOL) packet that are to be in the buffer or indicate a timer that starts at a time of issuance of a first read request for a first segment of the packet in the buffer. In some examples, the jitter threshold level is not more than a maximum transmission unit (MTU) size associated with the buffer. In some examples, a fetch scheduler is used to adapt an amount of interface overspeed to reduce packet fetching latency while attempting to prevent fabric saturation based on a switch fabric load level, wherein the fetch scheduler is to control the jitter threshold level for the buffer by forcing a jitter threshold level based on switch fabric load level and latency profile of the switch fabric.

公开(公告)号：US11722438B2

公开(公告)日：2023-08-08

申请号：US16546993

申请日：2019-08-21

Applicant: Intel Corporation

Inventor： John Greth ,  Arvind Srinivasan ,  Robert Southworth ,  David Arditti Ilitzky ,  Bongjin Jung ,  Gaspar Mora Porta

IPC: H04L49/00 ,  H04L49/25 ,  H04L9/40 ,  H04L69/22 ,  H04L41/0896 ,  H04L49/90

CPC classification number: H04L49/3045 ,  H04L41/0896 ,  H04L49/257 ,  H04L49/9042 ,  H04L63/101 ,  H04L69/22

Abstract: Examples describe a manner of scheduling packet segment fetches at a rate that is based on one or more of: a packet drop indication, packet drop rate, incast level, operation of queues in SAF or VCT mode, or fabric congestion level. Headers of packets can be fetched faster than payload or body portions of packets and processed prior to queueing of all body portions. In the event a header is identified as droppable, fetching of the associated body portions can be halted and any body portion that is queued can be discarded. Fetch overspeed can be applied for packet headers or body portions associated with packet headers that are approved for egress.

公开(公告)号：US11700209B2

公开(公告)日：2023-07-11

申请号：US16727543

申请日：2019-12-26

Applicant: Intel Corporation

Inventor： Robert Southworth ,  Karl S. Papadantonakis ,  Mika Nystroem ,  Arvind Srinivasan ,  David Arditti Ilitzky ,  Jonathan Dama

IPC: H04L47/625 ,  H04L49/901 ,  H04L67/568

CPC classification number: H04L47/6255 ,  H04L49/901 ,  H04L67/568

Abstract: Examples describe use of multiple meta-data delivery schemes to provide tags that describe packets to an egress port group. A tag, that is smaller than a packet, can be associated with a packet. The tag can be stored in a memory, as a group with other tags, and the tag can be delivered to a queue associated with an egress port. Packets received at an ingress port can be as non-interleaved to reduce underrun and providing cut-through to an egress port. A shared memory can be allocated to store packets received at a single ingress port or shared to store packets from multiple ingress ports.

公开(公告)号：US11575609B2

公开(公告)日：2023-02-07

申请号：US16517358

申请日：2019-07-19

Applicant: Intel Corporation

Inventor： Arvind Srinivasan ,  Ramakrishna Huggahalli ,  Parthasarathy Sarangam ,  Sunil Ahluwalia ,  Mrittika Ganguli ,  Malek Musleh

IPC: H04L47/2441 ,  H04L47/122 ,  H04L47/11

Abstract: A switch or network interface can detect congestion caused by a flow of packets. The switch or network interface can generate a congestion hint packet and send the congestion hint packet directly to a source transmitter of the flow of packets that caused the congestion. The congestion hint packet can include information that the source transmitter can use to determine a remedial action to attempt to alleviate or stop congestion at the switch or network interface. For example, the transmitter can reduce a transmit rate of the flow of packets and/or select another route for the flow of packets. Some or all switches or network interfaces between the source transmitter and a destination endpoint can employ flow differentiation whereby a queue is selected to accommodate for a flow's sensitivity to latency.

公开(公告)号：US11531752B2

公开(公告)日：2022-12-20

申请号：US16142693

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Akeem Abodunrin ,  Lev Faerman ,  Scott Dubal ,  Suyog Kulkarni ,  Anjali Singhai Jain ,  Eliel Louzoun ,  Nrupal Jani ,  Yadong Li ,  Eliezer Tamir ,  Arvind Srinivasan ,  Ben-Zion Friedman

IPC: G06F21/55 ,  G06F13/40 ,  G06F21/53

Abstract: Technologies for control plane separation at a network interface controller (NIC) of a compute device configured to transmit, by a resource of the compute device, commands to a physical function managed by a network interface controller (NIC) of the compute device. The NIC is further to establish a data plane separate from a control plane, wherein the control plane comprises one of the trusted control path and the untrusted control path. Additionally, the resource is configured to transmit the commands via one of the trusted control path or the untrusted control path based on a trust level associated with the physical function. Other embodiments are described herein.

公开(公告)号：US11381515B2

公开(公告)日：2022-07-05

申请号：US16550007

申请日：2019-08-23

Applicant: Intel Corporation

Inventor： Arvind Srinivasan ,  Robert Southworth ,  Helia A. Naeimi

IPC: H04L47/625 ,  H04L47/11 ,  H04L47/32

Abstract: Examples herein relate to allocation of an intermediate queue to a flow or traffic class (or other allocation) of packets prior to transmission to a network. Various types of intermediate queues are available for selection. An intermediate queue can be shallow and have an associated throughput that attempts to meet or exceed latency guarantees for a packet flow or traffic class. Another intermediate queue is larger in size and expandable and can be used for packets that are sensitive to egress port incast such as latency sensitive packets. Yet another intermediate queue is expandable but provides no guarantee on maximum end-to-end latency and can be used for packets where dropping is to be avoided. Intermediate queues can be deallocated after a flow or traffic class ends and related memory space can be used for another intermediate queue.