Invention Grant
- Patent Title: Parallel bit interleaver
-
Application No.: US17398273Application Date: 2021-08-10
-
Publication No.: US11671118B2Publication Date: 2023-06-06
- Inventor: Mihail Petrov
- Applicant: Panasonic Corporation
- Applicant Address: JP Osaka
- Assignee: PANASONIC HOLDINGS CORPORATION
- Current Assignee: PANASONIC HOLDINGS CORPORATION
- Current Assignee Address: JP Osaka
- Agency: Wenderoth, Lind & Ponack, L.L.P.
- Priority: EP 004127 2011.05.18
- Main IPC: H03M13/27
- IPC: H03M13/27 ; H03M13/11 ; H03M13/25 ; H03M13/29 ; H03M13/35 ; H03M13/00 ; H04L1/00 ; H04L1/06

Abstract:
A bit interleaving method involves applying a bit permutation process to bits of a QC-LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword after the permutation process into a plurality of constellation words each including M bits, the codeword being divided into F×N′/M folding sections (N′ being a subset of N selected cyclic blocks and being a multiple of M/F), each of the constellation words being associated with one of the F×N′/M folding sections, and the bit permutation process being applied such that each of the constellation words includes F bits from each of M/F different cyclic blocks in a given folding section associated with a given constellation word.
Public/Granted literature
- US20210367618A1 PARALLEL BIT INTERLEAVER Public/Granted day:2021-11-25
Information query
IPC分类: