Invention Grant
- Patent Title: Selective sampling of a data unit during a program erase cycle based on error rate change patterns
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Application No.: US17461918Application Date: 2021-08-30
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Publication No.: US11698832B2Publication Date: 2023-07-11
- Inventor: Harish R Singidi , Ashutosh Malshe , Vamsi Pavan Rayaprolu , Kishore Kumar Muchherla
- Applicant: MICRON TECHNOLOGY, INC.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Lowenstein Sandler LLP
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F11/10 ; G06F11/07 ; G06F12/0882 ; G06F11/30 ; G06F12/02

Abstract:
A processing device, operatively coupled with the memory device, is configured to determine a first error rate associated a first set of pages of a plurality of pages of a data unit of a memory device, and a second error rate associated with a second set of pages of the plurality of pages of the data unit, determine a first pattern of error rate change for the data unit based on the first error rate and the second error rate, and responsive to determining that the first pattern of error rate change corresponds to a predetermined second pattern of error rate change, perform an action pertaining to defect remediation with respect to the data unit.
Public/Granted literature
- US20210390016A1 SELECTIVE SAMPLING OF A DATA UNIT DURING A PROGRAM ERASE CYCLE BASED ON ERROR RATE CHANGE PATTERNS Public/Granted day:2021-12-16
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