公开(公告)号：US11561722B2

公开(公告)日：2023-01-24

申请号：US17002374

申请日：2020-08-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Harish R Singidi ,  Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Kishore Kumar Muchherla

IPC: G06F3/06 ,  H03M7/30 ,  G06F11/10

Abstract: A processing device, operatively coupled with a memory device, is configured to perform a write operation on a page of a plurality of pages of a data unit of a memory device, to store host data in the page of the data unit. The processing device further generates a parity page for the host data stored in the page of the data unit and adds the parity page to parity data stored at a parity data storage location. Responsive to determining that a first size of the stored parity data satisfies a first condition, the processing device initiates execution of a compression algorithm to compress the stored parity data. Responsive to determining that a second size of the parity data resulting from the execution of the compression algorithm satisfies a second condition, the processing device performs a scan operation to release at least a subset of the stored parity data.

公开(公告)号：US20230153011A1

公开(公告)日：2023-05-18

申请号：US18098279

申请日：2023-01-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Harish R Singidi ,  Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Kishore Kumar Muchherla

IPC: G06F3/06 ,  H03M7/30 ,  G06F11/10

CPC classification number: G06F3/0652 ,  G06F3/0608 ,  H03M7/6011 ,  G06F11/1004 ,  G06F3/0679

Abstract: A processing device, operatively coupled with a memory device, is configured to perform a write operation on a page of a plurality of pages of a data unit of a memory device. The processing device further generates a parity page for data stored in the page of the data unit and associates the parity page with parity data associated with the data unit. Responsive to determining that a first size of the parity data is larger than a first threshold size, the processing device compresses the parity data. Responsive to determining that a second size of the compressed parity data is larger than a second threshold size, the processing device releases at least a subset of the parity data corresponding to a subset of the data that is free from defects.

公开(公告)号：US11698832B2

公开(公告)日：2023-07-11

申请号：US17461918

申请日：2021-08-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Harish R Singidi ,  Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Kishore Kumar Muchherla

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/07 ,  G06F12/0882 ,  G06F11/30 ,  G06F12/02

CPC classification number: G06F11/1068 ,  G06F11/076 ,  G06F11/0793 ,  G06F11/3037 ,  G06F12/0246 ,  G06F12/0882

Abstract: A processing device, operatively coupled with the memory device, is configured to determine a first error rate associated a first set of pages of a plurality of pages of a data unit of a memory device, and a second error rate associated with a second set of pages of the plurality of pages of the data unit, determine a first pattern of error rate change for the data unit based on the first error rate and the second error rate, and responsive to determining that the first pattern of error rate change corresponds to a predetermined second pattern of error rate change, perform an action pertaining to defect remediation with respect to the data unit.

公开(公告)号：US11182237B1

公开(公告)日：2021-11-23

申请号：US17000062

申请日：2020-08-21

Applicant: Micron Technology, Inc.

Inventor： Harish R Singidi ,  Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Kishore Kumar Muchherla

IPC: G06F11/00 ,  G06F11/07 ,  G11C29/00

Abstract: A processing device, operatively coupled with the memory device, is configured to perform an operation on a page of a plurality of pages of a data unit of the memory device to modify data on the page. The processing device also determines a first operation execution time of the page upon performing the operation on the page of the data unit. The processing device further determines whether the first operation execution time satisfies a condition that is based on a predetermined second operation execution time, the predetermined second operation execution time is indicative of lack of defect in at least one other data unit. Lastly, responsive to determining that the first operation execution time satisfies the condition, the processing device performs a scan operation of at least a subset of the plurality of pages of the data unit to decide whether the data unit has a defect.

公开(公告)号：US11928353B2

公开(公告)日：2024-03-12

申请号：US18098279

申请日：2023-01-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Harish R Singidi ,  Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Kishore Kumar Muchherla

IPC: G06F3/06 ,  G06F11/10 ,  H03M7/30

CPC classification number: G06F3/0652 ,  G06F3/0608 ,  G06F3/0679 ,  G06F11/1004 ,  H03M7/6011

Abstract: A processing device, operatively coupled with a memory device, is configured to perform a write operation on a page of a plurality of pages of a data unit of a memory device. The processing device further generates a parity page for data stored in the page of the data unit and associates the parity page with parity data associated with the data unit. Responsive to determining that a first size of the parity data is larger than a first threshold size, the processing device compresses the parity data. Responsive to determining that a second size of the compressed parity data is larger than a second threshold size, the processing device releases at least a subset of the parity data corresponding to a subset of the data that is free from defects.

公开(公告)号：US11106532B1

公开(公告)日：2021-08-31

申请号：US16862446

申请日：2020-04-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Harish R Singidi ,  Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Kishore Kumar Muchherla

IPC: G06F11/00 ,  G11C29/00 ,  G06F11/10 ,  G06F11/07 ,  G06F12/0882 ,  G06F11/30 ,  G06F12/02

Abstract: A processing device, operatively coupled with the memory device, is configured to perform a first program erase cycle (PEC) on a data unit of a memory device, wherein performing the first PEC comprises scanning a first set of pages of a plurality of pages of the data unit to determine a first error rate. The processing device also determines a first pattern of error rate change for the data unit based on the first error rate and a second error rate. The processing device then compares the first pattern of error rate change for the data unit with a predetermined pattern of error rate that is indicative of a defect. Responsive to determining that the first pattern of error rate change corresponds to the predetermined pattern of error rate change, the processing device performs an action pertaining to defect remediation with respect to the data unit.