Invention Grant
- Patent Title: Multi-level wear leveling for non-volatile memory
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Application No.: US16947291Application Date: 2020-07-27
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Publication No.: US11704024B2Publication Date: 2023-07-18
- Inventor: Ying Yu Tai , Ning Chen , Jiangli Zhu
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Lowenstein Sandler LLP
- Main IPC: G06F3/06
- IPC: G06F3/06 ; G06F12/10

Abstract:
A memory sub-system performs a first media management operation among a plurality of individual data units of a memory device after a first interval, the first media management operation comprising a first algebraic mapping function, and performs a second media management operation among a first plurality of groups of data units of the memory device after a second interval, wherein a first group of the first plurality of groups comprises the plurality of individual data units, the second media management operation comprising a second algebraic mapping function.
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