Invention Grant
- Patent Title: Enabling a multi-chip daisy chain topology using peripheral component interconnect express (PCIe)
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Application No.: US17564975Application Date: 2021-12-29
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Publication No.: US11714776B2Publication Date: 2023-08-01
- Inventor: Kishon Vijay Abraham Israel Vijayponraj , Sriramakrishnan Govindarajan , Mihir Narendra Mody
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: Texas Instmments Incorporated
- Current Assignee: Texas Instmments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Brian D. Graham; Frank D. Cimino
- Priority: IN 2141035280 2021.08.05
- Main IPC: G06F13/42
- IPC: G06F13/42 ; G06F9/4401 ; G06F13/40 ; G06F12/1027

Abstract:
A system-on-chip (SoC) may be configured to enable a Multi-Chip Daisy Chain Topology using peripheral component interface express (PCIe). The SoC may include a processor, a local memory, a root complex operably connected to the processor and the local memory, and a multi-function endpoint controller. The root complex may obtain forwarding information to configure routing of transactions to one or more PCIe endpoint functions or to the local memory. The root complex may initialize, based on the forwarding information, access between a host and the one or more PCIe endpoint functions. The multi-function endpoint controller may obtain a descriptor and endpoint information to configure outbound portals for transactions to at least one remote host. The multi-function endpoint controller may establish a communication path between the host and a function out of a plurality of functions.
Public/Granted literature
- US20230041617A1 Enabling a Multi-Chip Daisy Chain Topology using Peripheral Component Interconnect Express (PCIe) Public/Granted day:2023-02-09
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