Invention Grant
- Patent Title: Localized stress regions for three-dimension chiplet formation
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Application No.: US17473248Application Date: 2021-09-13
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Publication No.: US11721551B2Publication Date: 2023-08-08
- Inventor: Anton J. Devilliers , Daniel J. Fulford , Anthony R. Schepis , Mark I. Gardner , H. Jim Fulford
- Applicant: Tokyo Electron Limited
- Applicant Address: JP Tokyo
- Assignee: Tokyo Electron Limited
- Current Assignee: Tokyo Electron Limited
- Current Assignee Address: JP Tokyo
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Main IPC: H01L21/027
- IPC: H01L21/027 ; H01L23/16 ; H01L23/498

Abstract:
Aspects of the present disclosure provide a method for forming a chiplet onto a semiconductor structure. For example, the method can include providing a first semiconductor structure having a first circuit and a first wiring structure formed on a first side thereof. The method can further include attaching the first side of the first semiconductor structure to a carrier substrate. The method can further include forming a stress film on a second side of the first semiconductor structure. The method can further include separating the carrier substrate from the first semiconductor structure. The method can further include cutting the stress film and the first semiconductor structure to define at least one chiplet. The method can further include bonding the at least one chiplet to a second semiconductor structure having a second circuit and a second wiring structure such that the second wiring structure is connected to the first wiring structure.
Public/Granted literature
- US20220238328A1 LOCALIZED STRESS REGIONS FOR THREE-DIMENSION CHIPLET FORMATION Public/Granted day:2022-07-28
Information query
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