公开(公告)号：US12276922B2

公开(公告)日：2025-04-15

申请号：US17198936

申请日：2021-03-11

Applicant: Tokyo Electron Limited

Inventor： Daniel Fulford ,  Anton J. Devilliers

IPC: G03F7/00 ,  G03F7/09 ,  H01L21/02 ,  H01L21/66 ,  H01L21/67 ,  H01L23/00

Abstract: A method of microfabrication is provided. A substrate having a working surface and having a backside surface opposite to the working surface is received. The substrate has an initial wafer bow resulting from one or more micro fabrication processing steps executed on the working surface of the substrate. The initial wafer bow of the substrate is measured and the initial wafer bow is used to generate an initial wafer bow value that identifies a degree of first order wafer bowing of the substrate. A correction film recipe based on the initial wafer bow value is identified. The correction film recipe specifies parameters of a correction film to be deposited on the backside surface of the substrate to change wafer bow of the substrate from the initial wafer bow to a modified wafer bow. The correction film on the backside surface of the substrate according to the correction film recipe is deposited. The correction film physically modifies internal stresses on the substrate and causes the substrate to have a modified bow with the predetermined wafer bow value.

公开(公告)号：US10586765B2

公开(公告)日：2020-03-10

申请号：US16011377

申请日：2018-06-18

Applicant: Tokyo Electron Limited

Inventor： Jeffrey Smith ,  Anton J. Devilliers ,  Kandabara Tapily

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/762 ,  H01L29/06 ,  H01L23/532 ,  H01L21/8238 ,  H01L21/822 ,  H01L29/78 ,  H01L21/74 ,  H01L27/06 ,  H01L27/092 ,  H01L29/775 ,  H01L29/66

Abstract: Aspects of the disclosure provide a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes a power rail formed in an isolation trench. The power rail is covered by a dielectric cap that isolates the power rail from conductive pattern structures on the dielectric cap. Further, an opening is selectively formed in the dielectric cap and is filled with conductive material to selectively connect a conductive pattern structure with the power rail.

公开(公告)号：US11862497B2

公开(公告)日：2024-01-02

申请号：US17381297

申请日：2021-07-21

Applicant: Tokyo Electron Limited

Inventor： H. Jim Fulford ,  Anthony Schepis ,  Anton J. Devilliers

IPC: H01L23/48 ,  H01L21/67 ,  H01L23/544 ,  H01L21/027 ,  H01L23/528

CPC classification number: H01L21/67282 ,  H01L21/0275 ,  H01L23/528 ,  H01L23/544 ,  H01L2223/5444

Abstract: A method for marking a semiconductor substrate at the die level for providing unique authentication and serialization includes projecting a first pattern of actinic radiation onto a layer of photoresist on the substrate using mask-based photolithography, the first pattern defining semiconductor device structures and projecting a second pattern of actinic radiation onto the layer of photoresist using direct-write projection, the second pattern defining a unique wiring structure having a unique electrical signature.

公开(公告)号：US11616053B2

公开(公告)日：2023-03-28

申请号：US16559923

申请日：2019-09-04

Applicant: Tokyo Electron Limited

Inventor： Jeffrey Smith ,  Anton J. Devilliers ,  Kandabara Tapily

IPC: H01L29/417 ,  H01L27/02 ,  H01L27/092

Abstract: A semiconductor device includes: a substrate having a surface, the surface being planar; a first logic gate provided on the substrate and comprising a first field effect transistor (FET) having a first channel, and a first pair of source-drain regions; a second logic gate stacked over the first logic gate along a vertical direction perpendicular to the surface of the substrate, the second logic gate comprising a second FET having a second channel, and a second pair of source-drain regions; and a contact electrically connecting a source-drain region of the first FET to a source-drain region of the second FET such that at least a portion of current flowing between the first and second logic gate will flow along said vertical direction.

公开(公告)号：US11460775B2

公开(公告)日：2022-10-04

申请号：US16560776

申请日：2019-09-04

Applicant: Tokyo Electron Limited

Inventor： Hoyoung Kang ,  Anton J. Devilliers ,  Corey Lemley

IPC: G03F7/16 ,  B08B17/02

Abstract: Methods for processing a substrate are provided. The method includes receiving a substrate. The substrate has a front side surface, a backside surface, and a side edge surface. The method also includes forming a first material in a first annular region of the front side surface, resulting in the first annular being coated with the first material. The first annular region is immediately adjacent to a perimeter of the substrate. The first annular region has a first outer perimeter proximate to the perimeter of the substrate and a first inner perimeter away from the perimeter of the substrate. The method also includes forming a second material in an interior region of the front side surface, the second material coating the front side surface without adhering to the annular region.

公开(公告)号：US11171208B2

公开(公告)日：2021-11-09

申请号：US16848738

申请日：2020-04-14

Applicant: Tokyo Electron Limited

Inventor： H. Jim Fulford ,  Mark I. Gardner ,  Anton J. Devilliers

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8239

Abstract: Transistor/semiconductor devices and methods of forming transistor/semiconductor devices. The devices include a metal layer with dielectric isolation within existing 3D silicon stacks. Two different disposable materials within the 3D silicon stack are selectively removed later from other layers in the stack to become future metal layers and oxide layer respectively, to provide the metal line isolated in a vertical central portion of the stack.

公开(公告)号：US20200152448A1

公开(公告)日：2020-05-14

申请号：US16679594

申请日：2019-11-11

Applicant: Tokyo Electron Limited

Inventor： Jodi GRZESKOWIAK ,  Anton J. Devilliers ,  Daniel Fulford

IPC: H01L21/02 ,  C09D179/08 ,  G03F7/30 ,  G03F7/20 ,  H01L21/768

Abstract: Techniques herein include methods of forming conformal films on substrates including semiconductor wafers. Conventional film forming techniques can be slow and expensive. Methods herein include depositing a self-assembled monolayer (SAM) film over the substrate. The SAM film can include an acid generator configured to generate acid in response to a predetermined stimulus. A polymer film is deposited over the SAM film. The polymer film is soluble to a predetermined developer and configured to change solubility in response to exposure to the acid. The acid generator is stimulated and generates acid. The acid is diffused into the polymer film. The polymer film is developed with the predetermined developer to remove portions of the polymer film that are not protected from the predetermined developer. These process steps can be repeated a desired number of times to grow an aggregate film layer by layer.

公开(公告)号：US11883837B2

公开(公告)日：2024-01-30

申请号：US17196189

申请日：2021-03-09

Applicant: Tokyo Electron Limited

Inventor： Mirko Vukovic ,  Daniel Fulford ,  Anton J. Devilliers

IPC: B05B12/08 ,  G01B11/06 ,  H01L21/67 ,  G01N21/55 ,  G01N21/84

CPC classification number: B05B12/084 ,  G01B11/0625 ,  H01L21/6715 ,  H01L21/67253 ,  G01N2021/556 ,  G01N2021/8427

Abstract: Light can be used to monitor coating a liquid on a substrate. By directing the light to a spot on the substrate, when the liquid passes through the spot, some light will be reflected, while some light will be scattered. Monitoring this behavior can indicate whether a substrate has been successfully coated with the liquid, as well as identifying defects. Further, coating times can be monitored to make process adjustments.

公开(公告)号：US11841617B2

公开(公告)日：2023-12-12

申请号：US17023470

申请日：2020-09-17

Applicant: Tokyo Electron Limited

Inventor： Anton J. Devilliers ,  Jodi Grzeskowiak ,  Daniel Fulford ,  Richard A. Farrell ,  Jeffrey Smith

IPC: G03F7/039 ,  H01L21/027 ,  G03F7/20 ,  G03F7/30 ,  G03F7/16

CPC classification number: G03F7/039 ,  G03F7/16 ,  G03F7/2002 ,  G03F7/30 ,  H01L21/0274

Abstract: A method of forming a pattern on a substrate is provided. The method includes forming a first layer on an underlying layer of the substrate, where the first layer is patterned to have a first structure. The method also includes depositing a grafting material on side surfaces of the first structure, where the grafting material includes a solubility-shifting material. The method further includes diffusing the solubility-shifting material by a predetermined distance into a neighboring structure that abuts the solubility-shifting material, where the solubility-shifting material changes solubility of the neighboring structure in a developer, and removing soluble portions of the neighboring structure using the developer to form a second structure.

公开(公告)号：US11721551B2

公开(公告)日：2023-08-08

申请号：US17473248

申请日：2021-09-13

Applicant: Tokyo Electron Limited

Inventor： Anton J. Devilliers ,  Daniel J. Fulford ,  Anthony R. Schepis ,  Mark I. Gardner ,  H. Jim Fulford

IPC: H01L21/027 ,  H01L23/16 ,  H01L23/498

CPC classification number: H01L21/0274 ,  H01L23/16 ,  H01L23/49822

Abstract: Aspects of the present disclosure provide a method for forming a chiplet onto a semiconductor structure. For example, the method can include providing a first semiconductor structure having a first circuit and a first wiring structure formed on a first side thereof. The method can further include attaching the first side of the first semiconductor structure to a carrier substrate. The method can further include forming a stress film on a second side of the first semiconductor structure. The method can further include separating the carrier substrate from the first semiconductor structure. The method can further include cutting the stress film and the first semiconductor structure to define at least one chiplet. The method can further include bonding the at least one chiplet to a second semiconductor structure having a second circuit and a second wiring structure such that the second wiring structure is connected to the first wiring structure.