Invention Grant
- Patent Title: Ferroelectric capacitors with backend transistors
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Application No.: US16636199Application Date: 2017-09-29
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Publication No.: US11751402B2Publication Date: 2023-09-05
- Inventor: Abhishek A. Sharma
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2017/054603 2017.09.29
- International Announcement: WO2019/066967A 2019.04.04
- Date entered country: 2020-02-03
- Main IPC: H10B53/30
- IPC: H10B53/30 ; G11C7/18 ; G11C8/14 ; G11C11/22 ; H01L29/423

Abstract:
An integrated circuit includes a backend thin-film transistor (TFT) a ferroelectric capacitor electrically connected to the backend TFT. The backend TFT has a gate electrode, source and drain regions, a semiconductor region between and physically connecting the source and drain regions, and a gate dielectric between the gate electrode and semiconductor region. The ferroelectric capacitor has a first terminal electrically connected to one of the source and drain regions, a second terminal, and a ferroelectric dielectric between the first and second terminals. In an embodiment, a memory cell includes this integrated circuit, the gate electrode being electrically connected to a wordline, the source region being electrically coupled to a bitline, and the drain region being the one of the source and drain regions. In an embodiment, an embedded memory includes wordlines, bitlines, and a plurality of such memory cells at crossing regions of the wordlines and bitlines.
Public/Granted literature
- US20200373312A1 FERROELECTRIC CAPACITORS WITH BACKEND TRANSISTORS Public/Granted day:2020-11-26
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