Invention Grant
- Patent Title: E-D mode 2DEG FET with gate spacer to locally tune VT and improve breakdown
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Application No.: US16218882Application Date: 2018-12-13
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Publication No.: US11757027B2Publication Date: 2023-09-12
- Inventor: Rahul Ramaswamy , Nidhi Nidhi , Walid M. Hafez , Johann C. Rode , Paul Fischer , Han Wui Then , Marko Radosavljevic , Sansaptak Dasgupta
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L29/778
- IPC: H01L29/778 ; H01L29/66 ; H01L29/78 ; H01L27/06 ; H01L21/8236 ; H01L21/8252 ; H01L21/8234 ; H01L27/088

Abstract:
Embodiments include a transistor and methods of forming such transistors. In an embodiment, the transistor comprises a semiconductor substrate, a barrier layer over the semiconductor substrate; a polarization layer over the barrier layer, an insulating layer over the polarization layer, a gate electrode through the insulating layer and the polarization layer, a spacer along sidewalls of the gate electrode, and a gate dielectric between the gate electrode and the barrier layer.
Information query
IPC分类: