Invention Grant
- Patent Title: Multi-member test probe structure
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Application No.: US17343648Application Date: 2021-06-09
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Publication No.: US11774489B2Publication Date: 2023-10-03
- Inventor: Pooya Tadayon , Justin Huttula
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Essential Patents Group, LLP
- Main IPC: G01R31/28
- IPC: G01R31/28 ; G01R3/00 ; G01R1/067

Abstract:
A testing arrangement for testing Integrated Circuit (IC) interconnects is provided. In an example, the testing arrangement includes a substrate, and a first interconnect structure. The first interconnect structure may include a first member having a first end to attach to the substrate and a second end opposite the first end, and a second member having a first end to attach to the substrate and a second end opposite the first end. In some examples, the second end of the first member and the second end of the second member are to contact a second interconnect structure of a IC device under test, and the first end of the first member and the first end of the second member are coupled such that the first member and the second member are to transmit, in parallel, current to the second interconnect structure of the IC device under test.
Public/Granted literature
- US20210302489A1 MULTI-MEMBER TEST PROBE STRUCTURE Public/Granted day:2021-09-30
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