Invention Grant
- Patent Title: Semiconductor structure and method of forming the same
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Application No.: US17472912Application Date: 2021-09-13
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Publication No.: US11839076B2Publication Date: 2023-12-05
- Inventor: Che-Fu Chuang , Hsiu-Han Liao
- Applicant: Winbond Electronics Corp.
- Applicant Address: TW Taichung
- Assignee: WINBOND ELECTRONICS CORP.
- Current Assignee: WINBOND ELECTRONICS CORP.
- Current Assignee Address: TW Taichung
- Agency: Muncy, Geissler, Olds & Lowe, P.C.
- Priority: TW 0112231 2021.04.01
- Main IPC: H10B41/47
- IPC: H10B41/47 ; H10B41/46 ; H10B41/44

Abstract:
A method of forming a semiconductor structure includes forming first to third sacrificial layers on a substrate including a memory cell area and a peripheral area with a word line area. The second and third sacrificial layers in the word line area are removed to expose the top surface of the first sacrificial layer. The first sacrificial layer in the word line area and the third sacrificial layer in the memory cell area are removed. A word line dielectric layer and a first conductive layer are formed on the substrate in the word line area. The first and second sacrificial layers in the memory cell area are removed. A tunneling dielectric layer is formed on the substrate in the memory cell area. The thickness of the tunneling dielectric layer is smaller than the thickness of the word line dielectric layer.
Public/Granted literature
- US20220320127A1 SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME Public/Granted day:2022-10-06
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