Invention Grant
- Patent Title: Mid-processing removal of semiconductor fins during fabrication of integrated circuit structures
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Application No.: US16631345Application Date: 2017-09-18
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Publication No.: US11887860B2Publication Date: 2024-01-30
- Inventor: Mehmet O. Baykan , Anurag Jain , Szuya S. Liao
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2017/052002 2017.09.18
- International Announcement: WO2019/055041A 2019.03.21
- Date entered country: 2020-01-15
- Main IPC: H01L21/308
- IPC: H01L21/308 ; H01L27/092 ; H01L21/8238 ; H01L29/10 ; H01L29/161 ; H01L29/20

Abstract:
Techniques are disclosed for forming integrated circuit structures having a plurality of semiconductor fins, which in turn can be used to form non-planar transistor structures. The techniques include a mid-process removal of one or more partially-formed fins. The resulting integrated circuit structure includes a plurality of semiconductor fins having relatively uniform dimensions (e.g., fin width and trough depth). In an embodiment, the fin forming procedure includes partially forming a plurality of fins, using a selective etch stop built into the semiconductor structure in which the fins are being formed. One or more of the partially-formed fins are removed via sacrificial fin cut mask layer(s). After fin removal, the process continues by further etching trenches between the partially-formed fins (deep etch) to form portion of fins that will ultimately include transistor channel portion. A liner material may be deposited to protect the partially-formed fins during this subsequent deep trench etch.
Public/Granted literature
- US20200227267A1 MID-PROCESSING REMOVAL OF SEMICONDUCTOR FINS DURING FABRICATION OF INTEGRATED CIRCUIT STRUCTURES Public/Granted day:2020-07-16
Information query
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