Invention Grant
- Patent Title: Power enhanced stacked chip scale package solution with integrated die attach film
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Application No.: US17714979Application Date: 2022-04-06
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Publication No.: US11894344B2Publication Date: 2024-02-06
- Inventor: Zhijun Xu , Bin Liu , Yong She , Zhicheng Ding
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Essential Patents Group, LLP
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L23/00 ; H01L25/18 ; H01L25/00

Abstract:
An apparatus comprising: a die stack comprising at least one die pair, the at least one die pair having a first die over a second die, the first die and the second die both having a first surface and a second surface, the second surface of the first die over the first surface of the second die; and an adhesive film between the first die and the second die of the at least one die pair; wherein the adhesive film comprises an insulating layer and a conductive layer, the insulating layer adhering to the second surface of the first die and the conductive layer adhering to the first surface of the second die.
Public/Granted literature
- US20220230995A1 POWER ENHANCED STACKED CHIP SCALE PACKAGE SOLUTION WITH INTEGRATED DIE ATTACH FILM Public/Granted day:2022-07-21
Information query
IPC分类: