Invention Grant
- Patent Title: Stacked trigate transistors with dielectric isolation and process for forming such
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Application No.: US18095973Application Date: 2023-01-11
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Publication No.: US11894372B2Publication Date: 2024-02-06
- Inventor: Willy Rachmady , Cheng-Ying Huang , Gilbert Dewey , Aaron Lilak , Patrick Morrow , Anh Phan , Ehren Mannebach , Jack T. Kavalieros
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Wuilliamson & Wyatt, P.C.
- The original application number of the division: US16455667 2019.06.27
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L27/088 ; H01L29/66
Abstract:
A device is disclosed. The device includes a first semiconductor fin, a first source-drain epitaxial region adjacent a first portion of the first semiconductor fin, a second source-drain epitaxial region adjacent a second portion of the first semiconductor fin, a first gate conductor above the first semiconductor fin, a gate spacer covering the sides of the gate conductor, a second semiconductor fin below the first semiconductor fin, a second gate conductor on a first side of the second semiconductor fin and a third gate conductor on a second side of the second semiconductor fin, a third source-drain epitaxial region adjacent a first portion of the second semiconductor fin, and a fourth source-drain epitaxial region adjacent a second portion of the second semiconductor fin. The device also includes a dielectric isolation structure below the first semiconductor fin and above the second semiconductor fin that separates the first semiconductor fin and the second semiconductor fin.
Public/Granted literature
- US20230170350A1 STACKED TRIGATE TRANSISTORS WITH DIELECTRIC ISOLATION AND PROCESS FOR FORMING SUCH Public/Granted day:2023-06-01
Information query
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