Invention Grant
- Patent Title: Double-gated ferroelectric field-effect transistor
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Application No.: US17673670Application Date: 2022-02-16
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Publication No.: US11895846B2Publication Date: 2024-02-06
- Inventor: Abhishek A. Sharma , Brian S. Doyle , Ravi Pillarisetty , Prashant Majhi , Elijah V. Karpov
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe Williamson & Wyatt, P.C.
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H10B51/30 ; G11C11/22 ; H01L29/51 ; H01L29/78

Abstract:
A ferroelectric field-effect transistor (FeFET) includes first and second gate electrodes, source and drain regions, a semiconductor region between and physically connecting the source and drain regions, a first gate dielectric between the semiconductor region and the first gate electrode, and a second gate dielectric between the semiconductor region and the second gate electrode. The first gate dielectric includes a ferroelectric dielectric. In an embodiment, a memory cell includes this FeFET, with the first gate electrode being electrically connected to a wordline and the drain region being electrically connected to a bitline. In another embodiment, a memory array includes wordlines extending in a first direction, bitlines extending in a second direction, and a plurality of such memory cells at crossing regions of the wordlines and the bitlines. In each memory cell, the wordline is a corresponding one of the wordlines and the bitline is a corresponding one of the bitlines.
Public/Granted literature
- US20220181335A1 DOUBLE-GATED FERROELECTRIC FIELD-EFFECT TRANSISTOR Public/Granted day:2022-06-09
Information query
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