Invention Grant
- Patent Title: Marker-based processor instruction grouping
-
Application No.: US16713432Application Date: 2019-12-13
-
Publication No.: US11900123B2Publication Date: 2024-02-13
- Inventor: Alexander Fuad Ashkar , Manu Rastogi , Harry J. Wise
- Applicant: ADVANCED MICRO DEVICES, INC.
- Applicant Address: US CA Santa Clara
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Santa Clara
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F9/38 ; G06T1/20 ; G06F15/80

Abstract:
A system includes a processing unit such as a GPU that itself includes a command processor configured to receive instructions for execution from a software application. A processor pipeline coupled to the processing unit includes a set of parallel processing units for executing the instructions in sets. A set manager is coupled to one or more of the processor pipeline and the command processor. The set manager includes at least one table for storing a set start time, a set end time, and a set execution time. The set manager determines an execution time for one or more sets of instructions of a first window of sets of instructions submitted to the processor pipeline. Based on the execution time of the one or more sets of instructions, a set limit is determined and applied to one or more sets of instructions of a second window subsequent to the first window.
Public/Granted literature
- US20210182072A1 MARKER-BASED PROCESSOR INSTRUCTION GROUPING Public/Granted day:2021-06-17
Information query