Invention Grant
- Patent Title: Semiconductor arrangement and method for making
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Application No.: US18111792Application Date: 2023-02-20
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Publication No.: US11901176B2Publication Date: 2024-02-13
- Inventor: Yi-Shan Chen , Hao-Heng Liu
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
- Applicant Address: TW Hsin-Chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
- Current Assignee Address: TW Hsin-Chu
- Agency: COOPER LEGAL GROUP, LLC
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L21/033

Abstract:
A method for fabricating a semiconductor arrangement is provided. The method includes forming a first dielectric layer and forming a first semiconductive layer over the first dielectric layer. The first semiconductive layer is patterned to form a patterned first semiconductive layer. The first dielectric layer is patterned using the patterned first semiconductive layer to form a patterned first dielectric layer. A second semiconductive layer is formed over the patterned first dielectric layer and the patterned first semiconductive layer.
Public/Granted literature
- US20230197439A1 SEMICONDUCTOR ARRANGEMENT AND METHOD FOR MAKING Public/Granted day:2023-06-22
Information query
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